Operating pulsed latches on a variable power supply
US-11112854-B2 · Sep 7, 2021 · US
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Warnock James D patents
Warnock James D is listed as an inventor on 59 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Warnock James D |
| Total patents | 59 |
| First publication | Mar 26, 2015 |
| Latest publication | Sep 7, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Priority based circuit synthesis
US-10678981-B2 · Jun 9, 2020 · US
Pessimism reduction in cross-talk noise determination used in integrated circuit design
US-10565336-B2 · Feb 18, 2020 · US
Pessimism reduction in cross-talk noise determination used in integrated circuit design
US-2019362045-A1 · Nov 28, 2019 · US
Operating pulsed latches on a variable power supply
US-2019286221-A1 · Sep 19, 2019 · US
Operating pulsed latches on a variable power supply
US-10386912-B2 · Aug 20, 2019 · US
Programmable clock division methodology with in-context frequency checking
US-10354046-B2 · Jul 16, 2019 · US
Debugging scan latch circuits using flip devices
US-10288678-B2 · May 14, 2019 · US
Adjusting scan connections based on scan control locations
US-10216885-B2 · Feb 26, 2019 · US
Priority based circuit synthesis
US-2019034563-A1 · Jan 31, 2019 · US
Recent patents
Latest publications not already listed above.
On-chip sensor for monitoring active circuits on integrated circuit (IC) chips
US-10191108-B2 · Jan 29, 2019 · US
Priority based circuit synthesis
US-10133840-B2 · Nov 20, 2018 · US
Programmable integrated circuit standard cell
US-10062709-B2 · Aug 28, 2018 · US
Operating pulsed latches on a variable power supply
US-2018196497-A1 · Jul 12, 2018 · US
Programmable integrated circuit standard cell
US-10002881-B2 · Jun 19, 2018 · US
Early analysis and mitigation of self-heating in design flows
US-9990454-B2 · Jun 5, 2018 · US
Programmable delay circuit including hybrid fin field effect transistors (finFETs)
US-9985616-B2 · May 29, 2018 · US
Adjusting scan connections based on scan control locations
US-2018096091-A1 · Apr 5, 2018 · US
Adjusting scan connections based on scan control locations
US-9934348-B2 · Apr 3, 2018 · US
Programmable integrated circuit standard cell
US-2018090513-A1 · Mar 29, 2018 · US
Programmable integrated circuit standard cell
US-2018090514-A1 · Mar 29, 2018 · US
Programmable clock division methodology with in-context frequency checking
US-2018068051-A1 · Mar 8, 2018 · US
Programmable clock division methodology with in-context frequency checking
US-9910954-B2 · Mar 6, 2018 · US
Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network
US-9891276-B2 · Feb 13, 2018 · US
Early analysis and mitigation of self-heating in design flows
US-2017351785-A1 · Dec 7, 2017 · US
Programmable clock division methodology with in-context frequency checking
US-2017344693-A1 · Nov 30, 2017 · US
Validating variation of timing constraint measurements
US-9760664-B2 · Sep 12, 2017 · US
Initializing scannable and non-scannable latches from a common clock buffer
US-9762213-B1 · Sep 12, 2017 · US
Initializing scannable and non-scannable latches from a common clock buffer
US-9762212-B1 · Sep 12, 2017 · US
Validating variation of timing constraint measurements
US-9760665-B2 · Sep 12, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 55 |
| Globalfoundries Inc | 3 |
| Globalfoundries Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2119/12 | 10 |
| H10D89/10 | 10 |
| G01R31/31723 | 8 |
| G06F30/367 | 8 |
| G06F30/3312 | 7 |