Debugging scan latch circuits using flip devices

Patent metadata

Field	Value
Publication number	US-10288678-B2
Application number	US-201715416203-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	May 7, 2015
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A latch circuit having a master latch and a slave latch includes a device used to short either the master latch or the slave latch. The device includes a transistor and a global control used to assert a signal, and is positioned to short an inverter of the master latch or the slave latch. When the signal is asserted by the global control, the inverter is shorted such that the output value of the inverter is the same as the input value. The assertion of the signal is facilitated by another device connected to the master latch and the slave latch that includes the global control and a transistor.

First claim

What is claimed is:

1. A circuit comprising:
an input portion;
a first circuit portion coupled to an output of the input portion;
a second circuit portion coupled to the first circuit portion;
an output portion coupled to an output of the second circuit portion;
a device coupled to at least one of the first circuit portion and the second circuit portion to selectively provide a short in the at least one of the first circuit portion and the second circuit portion, the short to provide a particular latch state, the particular latch state to be used to provide an output state at the output portion to be used in debugging the latch circuit; and
wherein:
the first circuit portion comprises a master latch and the second circuit portion comprises a slave latch;
the device is positioned to short the master latch; and
the master latch comprises a tri-state inverter and the device is positioned to short the tri-state inverter of the master latch, wherein an output of the tri-state inverter of the master latch is a same value as an input of the tri-state inverter of the master latch.

2. The circuit of claim 1 , wherein the device comprises one transistor and a global control to control the one transistor.

Assignees

• IBM

Inventors

• Warnock James D

Classifications

• G01R31/31705 Primary

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title