Early analysis and mitigation of self-heating in design flows

Patent metadata

Field	Value
Publication number	US-9990454-B2
Application number	US-201615172912-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Jun 3, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

First claim

The invention claimed is:

1. A method of reducing self-heating in semiconductor integrated circuit designs comprising:
accessing, at a processor unit, a logic and layout data representing a macro having an interconnection of one or more cells;
computing, at the processor unit, an effective thermal resistance value (Rth) for a cell of the macro based on a cell topology;
accessing, by the processor unit, activity data generated at a higher level of an integrated circuit design hierarchy;
generating, by the processor unit, based on said activity data, a workload specific to the macro;
determining, by the processor unit, from said macro specific workload, and based on a logic description of said macro, a workload specific Switching Factor (SF) value representing an amount of physical switching of an internal logic gate of the macro cell;
computing a change in temperature (deltaT) value using the Rth value and said SF value for a macro cell instance;
determining whether a deltaT value computed for the macro cell instance is in violation of a self-heating limit;
mitigating a self-heating of the macro cell design if a self-heating limit violation is detected; and
updating the layout data after mitigating of the self-heating.

2. The method of claim 1 , wherein said computing the deltaT value comprises:
calculating a power number value for the particular macro cell instance based on said switching factor value and a pre-determined power rule; and
using said power number value and said Rth value in said deltaT computing.

3. The method of claim 1 , wherein said self-heating limit is a pre-determined power budget, said method further comprising:
comparing said deltaT value against the pre-determined power budget to determine if the self-heating limit has been violated; and
optimizing the macro cell design to avoid the self-heating threshold violation.

4. The method of claim 1 , wherein said:
said higher level of a design hierarchy comprises a unit, a core, or a chip level.

5. The method of claim 1 , further comprising:
maintaining a mapping between logical and physical hierarchies.

6. The method of claim 2 , wherein said computing said Rth value considers a process, voltage and temperature condition applied to said cell.

7. The method of claim 1 , wherein for each cell of the macro, storing the Rth characterization values into the power rule associated with the standard cell, or storing the Rth characterization values in an off-line memory storage device.

8. The method of claim 1 , wherein a macro cell represents a FinFET device comprising: a number of fingers and a number of Fins, wherein said mitigating a self-heating of the macro cell design comprises one or more of: sharpening input slew rate at the cell, changing a power level of the macro cell, decreasing a number of Fins per cell finger, and changing a logic function of said macro.

9. A system of reducing self-heating in semiconductor integrated circuit designs comprising:
a memory storage device;
a processor unit in communication with said memory storage device and configure to:
access a logic and layout data representing a macro having an interconnection of one or more cells;
compute an effective thermal resistance value (Rth) for a cell of the macro based on a cell topology;
access activity data generated at a higher level of an integrated circuit design hierarchy;
generate based on said activity data, a workload specific to the macro;
determine from said macro specific workload, and based on a logic description of said macro, a workload specific Switching Factor (SF) value representing an amount of physical switching of an internal logic gate of the macro cell;
compute a change in temperature (deltaT) value using the Rth value and said SF value for a macro cell instance;
determine whether a deltaT value computed for the macro cell instance is in violation of a self-heating limit;
mitigate a self-heating of the macro cell design if a self-heating limit violation is detected; and
update the layout data after mitigating of the self-heating.

10. The system of claim 9 , wherein to compute the deltaT value, said processor unit is further configured to:
calculate a power number value for the particular macro cell instance based on said switching factor value and a pre-determined power rule; and
using said power number value and said Rth value in said deltaT computing.

11. The system of claim 9 , wherein said self-heating limit is a pre-determined power budget, said processor unit is further configured to:
compare said deltaT value against the pre-determined power budget to determine if the self-heating limit has been violated; and
optimize the macro cell design to avoid the self-heating threshold violation.

12. The system of claim 9 , wherein
said higher level of a design hierarchy comprises a unit, a core, or a chip level.

13. The system of claim 9 , wherein said processor unit is further configured to:
maintain a mapping between logical and physical hierarchies.

14. The system of claim 10 , wherein to compute said Rth value, said processor device is further configured to consider a process, voltage and temperature condition applied to said cell.

15. The system of claim 9 , wherein said processor device is further configured to: for each cell of the macro: storing the Rth characterization values into the power rule associated with the standard cell, or storing the Rth characterization values in an off-line memory storage device.

16. The system of claim 9 , wherein a macro cell represents a FinFET device, said cell topology comprising: a number of fingers and a number of Fins of said FinFET, wherein to mitigate a self-heating of the macro cell design, said processor device is further configured to one or more of: sharpen an input slew rate at a macro gate, change a power level of the macro gate, decrease a number of Fins per cell finger, and change a logic function of said macro.

17. A computer program product comprising a non-transitory computer readable storage medium storing a program of instructions executable by a machine to perform a method of reducing self-heating in semiconductor integrated circuit designs, the method comprising:
accessing a logic and layout data representing a macro having an interconnection of one or more cells;
computing an effective thermal resistance value (Rth) for a cell of the macro based on a cell topology;
accessing activity data generated at a higher level of an integrated circuit design hierarchy;
generating based on said activity data, a workload specific to the macro;
determining from said macro specific workload, and based on a logic description of said macro, a workload specific Switching Factor (SF) value representing an amount of physical switching of an internal logic gate of the macro cell;
computing a change in temperature (deltaT) value using the Rth value and said SF value for a macro cell instance;
determining whether a deltaT value computed for the macro cell instance is in violation of a self-heating limit;
mitigating a self-heating of the macro cell design if a self-heating limit violation is detected; and
updating the layout data after mitigating of the self-heating.

18. The computer readable storage medium as claimed in claim 17 , wherein said computing the deltaT value comprises:
calculating a power number value for the particular macro cell instance based on said switching factor value and a pre-determined power rule; and
using said power number value and said Rth value in said deltaT computing.

Assignees

• IBM

Inventors

• Dhanwada Nagashyamala R
• Dungan William W
• Joseph Arun
• Lee Sungjae
• Mets Arjen A
• Scheuermann Michael R
• Sigal Leon J
• Wachnick Richard A
• Warnock James D

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F17/5022

  Physics · mapped topic

• G06F17/505 Primary

  Physics · mapped topic