Operating pulsed latches on a variable power supply

Patent metadata

Field	Value
Publication number	US-11112854-B2
Application number	US-201916432524-A
Country	US
Kind code	B2
Filing date	Jun 5, 2019
Priority date	Jan 12, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

First claim

What is claimed is:

1. A method of operating pulsed latches on a variable power supply, the method comprising:
turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch, and wherein the first latch is a scan-only latch;
turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch;
performing a scan operation using the first latch and the second latch;
turning off the first power rail powering the first latch; and
responsive to completing the scan operation using the first latch and the second latch, performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

2. The method of claim 1 , wherein the first latch is one of a plurality of latches powered by the first power rail, and wherein the second latch is one of a plurality of latches powered by the second power rail.

3. The method of claim 1 , wherein the first latch and the second latch are directly connected such that no latch is between the first latch and the second latch.

4. The method of claim 1 , wherein turning off the first power rail powering the first latch comprises turning off components of the integrated circuit utilized during the scan operation and not utilized during the functional operation.

5. The method of claim 1 , wherein the first latch is operatively coupled to the second latch through isolation circuitry that prevents a current draw from the second latch to the first latch while the first power rail is off.

6. The method of claim 1 , wherein turning off the first power rail powering the first latch comprises turning off a plurality of power rails, wherein each of the plurality of power rails powers a plurality of scan-only latches.

7. The method of claim 1 , wherein the first power rail powers a scan data clock, and
wherein turning off the first power rail powering the first latch comprises turning off the scan data clock.

8. An apparatus for operating pulsed latches on a variable power supply, the apparatus comprising computer memory having disposed within it computer program instructions that, when executed, cause the apparatus to carry out the steps of:
turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch, and wherein the first latch is a scan-only latch;
turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch;
performing a scan operation using the first latch and the second latch;
turning off the first power rail powering the first latch; and
responsive to completing the scan operation using the first latch and the second latch, performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

9. The apparatus of claim 8 , wherein the first latch is one of a plurality of latches powered by the first power rail, and wherein the second latch is one of a plurality of latches powered by the second power rail.

10. The apparatus of claim 8 , wherein the first latch and the second latch are directly connected such that no latch is between the first latch and the second latch.

11. The apparatus of claim 8 , wherein turning off the first power rail powering the first latch comprises turning off components of the integrated circuit utilized during the scan operation and not utilized during the functional operation.

12. The apparatus of claim 8 , wherein the first latch is operatively coupled to the second latch through isolation circuitry that prevents a current draw from the second latch to the first latch while the first power rail is off.

13. The apparatus of claim 8 , wherein turning off the first power rail powering the first latch comprises turning off a plurality of power rails, wherein each of the plurality of power rails powers a plurality of scan-only latches.

14. The apparatus of claim 8 , wherein the first power rail powers a scan data clock, and
wherein turning off the first power rail powering the first latch comprises turning off the scan data clock.

15. A computer program product for operating pulsed latches on a variable power supply, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch, and wherein the first latch is a scan-only latch;
turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch;
performing a scan operation using the first latch and the second latch;
turning off the first power rail powering the first latch; and
responsive to completing the scan operation using the first latch and the second latch, performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation, wherein the first latch and the second latch are directly connected such that no latch is between the first latch and the second latch.

16. The computer program product of claim 15 , wherein the first latch is one of a plurality of latches powered by the first power rail, and wherein the second latch is one of a plurality of latches powered by the second power rail.

17. The computer program product of claim 15 , wherein turning off the first power rail powering the first latch comprises turning off components of the integrated circuit utilized during the scan operation and not utilized during the functional operation.

18. The computer program product of claim 15 , wherein the first latch is operatively coupled to the second latch through isolation circuitry that prevents a current draw from the second latch to the first latch while the first power rail is off.

19. The computer program product of claim 15 , wherein turning off the first power rail powering the first latch comprises turning off a plurality of power rails, wherein each of the plurality of power rails powers a plurality of scan-only latches.

Assignees

• IBM

Inventors

• Douskey Steven M
• Gopalakrishnasetty Raghu G
• Kusko Mary P
• Rajeev Hari Krishnan
• Warnock James D

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title