Programmable integrated circuit standard cell

Patent metadata

Field	Value
Publication number	US-10002881-B2
Application number	US-201715408753-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Sep 26, 2016
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.

First claim

What is claimed is:

1. A computer-implemented method of fabricating an integrated circuit (IC) by changing, within an IC design, a standard cell partially personalized by local wiring, the standard cell comprising a set of transistors, each transistor of the set of transistors having a fixed size and a fixed position within an established perimeter of the standard cell, the set of transistors at least partially interconnected to a set of local nodes by the local wiring located on a first local wiring layer, the standard cell further comprising a set of customization ports arranged on a global wiring layer and electrically connected to the set of local nodes, the standard cell further comprising a set of blockage shapes arranged to identify, on the global wiring layer, a set of areas reserved for personalization wiring, the personalization wiring configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, at least some customization ports of the set of customization ports in accordance with corresponding at least some blockage shapes of the set of blockage shapes, the method comprising:
personalizing the partially personalized standard cell according to a first logical function selected from among a set of logical functions, the personalizing according to the first logical function comprising:
assigning, to the partially personalized standard cell, a first function property corresponding to the first logical function; and
connecting, with a first set of personalization wiring, in accordance with the first function property, a first subset of customization ports of the set of customization ports according to a corresponding first subset of the set of blockage shapes; and

modifying the standard cell personalized according to the first logical function such that it is personalized according to a second logical function selected from among the set of logical functions rather than the first logical function, the modifying comprising:
replacing, in the standard cell personalized according to the first logical function, the assignment of the first logical function property with an assignment of second function property corresponding to the second logical function;
removing, from the global wiring layer of the standard cell personalized according to the first logical function, the first set of personalization wiring connected in accordance with the first function property; and
connecting, with a second set of personalization wiring, in accordance with the second function property, a second subset of customization ports of the set of customization ports according to a corresponding second subset of the set of blockage shapes; and

fabricating the IC, in accordance with the IC design, at a semiconductor manufacturing facility, the IC design including the standard cell that is personalized according to the second logical function.

Assignees

• IBM

Inventors

• Datta Ayan
• Shukla Ankur
• Warnock James D

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L2027/11888

  Electricity · mapped topic