Validating variation of timing constraint measurements

Patent metadata

Field	Value
Publication number	US-9760665-B2
Application number	US-201514833069-A
Country	US
Kind code	B2
Filing date	Aug 22, 2015
Priority date	Jul 7, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time. The information handling system compares the timing constraint sensitivity against a characterized sensitivity generated by a software modeling system and, when the timing constraint sensitivity does not match the characterized sensitivity, one or more of the software modeling system's modeling parameters are adjusted, causing the software modeling system to generate a changed characterized sensitivity of the circuit model.

First claim

The invention claimed is:

1. A method implemented by an information handling system that includes a memory and a processor, the method comprising:
executing a plurality of first sensitivity tests on a circuit model using a first signal arrival time value, the executing resulting in a plurality of first test results;
adjusting the first signal arrival time value to a second signal arrival time value in response to determining that the plurality of first test results do not meet a pre-determined probability threshold;
executing a plurality of second sensitivity tests on the circuit model using the second signal arrival time value, the executing resulting in a plurality of second test results;
in response to determining that the plurality of second test results meets the pre-determined probability threshold, computing a timing constraint sensitivity utilizing the second signal arrival time value;
determining whether the timing constraint sensitivity is within a pre-defined tolerance of a characterized sensitivity of the circuit model, wherein the characterized sensitivity was generated by a software modeling system during library characterization of the circuit model; and
adjusting one or more modeling parameters of the software modeling system based upon the determining, wherein the software modeling system generates a changed characterized sensitivity of the circuit model using the adjusted one or more modeling parameters.

2. The method of claim 1 wherein the plurality of sensitivity tests correspond to a setup test, and wherein the method further comprises:
wherein the first signal arrival time value is longer than the second signal arrival time value; and
decreasing the first signal arrival time value to the second signal arrival time value in response to determining that the plurality of first test results include an amount of test failures that is greater than the pre-determined probability threshold.

3. The method of claim 1 wherein the plurality of sensitivity tests correspond to a setup test, and wherein the method further comprises:
wherein the first signal arrival time value is shorter than the second signal arrival time value; and
increasing the first signal arrival time to the second signal arrival time in response to determining that the plurality of first test results includes an amount of test failures that is less than the pre-determined probability threshold.

4. The method of claim 1 wherein the plurality of sensitivity tests correspond to a hold test, and wherein the method further comprises:
wherein the first signal arrival time value is shorter than the second signal arrival time value; and
increasing the first signal arrival time value to the second signal arrival time value in response to determining that the plurality of first test results include an amount of test failures that is greater than the pre-determined probability threshold.

5. The method of claim 1 wherein the plurality of sensitivity tests correspond to a hold test, and wherein the method further comprises:
wherein the first signal arrival time value is longer than the second signal arrival time value; and
decreasing the first signal arrival time value to the second signal arrival time value in response to determining that the plurality of first test results include an amount of test failures that is less than the pre-determined probability threshold.

6. The method of claim 1 wherein the plurality of sensitivity tests correspond to a pulse width test, and wherein the method further comprises:
wherein the first signal arrival time value is longer than the second signal arrival time value; and
decreasing the first signal arrival time value to the second signal arrival time value in response to determining that the plurality of first test results include an amount of test failures that is greater than the pre-determined probability threshold.

7. The method of claim 1 wherein plurality of sensitivity tests correspond to a pulse width test, and wherein the method further comprises:
wherein the first signal arrival time value is shorter than the second signal arrival time value; and
increasing the first signal arrival time value to the second signal arrival time value in response to determining that the plurality of first test results include an amount of test failures that is less than the pre-determined probability threshold.

8. The method of claim 1 wherein:
the information handling system is a circuit model testing system;
the plurality of sensitivity tests are simulated on a Monte Carlo simulator that generate one or more actual test failures, the one or more actual test failures included in the plurality of first test results; and
the circuit model is a sequential circuit and each of the plurality of sensitivity tests has at least one unique across chip variation (ACV) parameter value.

9. The method of claim 1 wherein at least one of the one or more modeling parameters are selected from the group consisting of a technology model setting parameter, a circuit model configuration parameter, a simulation stimulus parameter, and a sensitivity measurement results calculation parameter.

10. The method of claim 1 further comprising:
utilizing the changed characterized sensitivity to perform a timing analysis on an integrated circuit that includes the circuit model, wherein the timing analysis produces one or more timing analysis test results.

Assignees

• IBM

Inventors

• Gupta Sachin K
• Rao Vasant B
• Skariah Suriya T
• Sundquist James E
• Warnock James D

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F17/5036 Primary

  Physics · mapped topic

• G06F17/5031

  Physics · mapped topic