Programmable clock division methodology with in-context frequency checking

Patent metadata

Field	Value
Publication number	US-10354046-B2
Application number	US-201715810314-A
Country	US
Kind code	B2
Filing date	Nov 13, 2017
Priority date	May 26, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

First claim

What is claimed is:

1. A method of using a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context, the method comprising:
setting up a timer;
determining, using a processor, a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value;
performing the timing analysis using the divide ratios of the one or more external clock dividers; and
generating the generalized macro timing abstract based on performing a detailed timing analysis of an associated macro using an initial timing context defined by a fastest expected clock.

2. The method according to claim 1 , wherein the determining the divide ratio of each external clock divider of the one or more external clock dividers as the function of another value includes determining the divide ratio according to a name of a timing signal corresponding with each external clock divider when the timing analysis is a hierarchical timing analysis involving more than one hierarchical level of a design of the integrated circuit.

3. The method according to claim 1 , wherein the determining the divide ratio of each external clock divider of the one or more external clock dividers as the function of another value includes determining the divide ratio based on a constraint at an input port of the generalized macro associated with each external clock divider.

4. The method according to claim 1 , wherein the determining the divide ratio of each external clock divider of the one or more external clock dividers as the function of another value includes determining the divide ratio for the generalized macro timing abstract based on a look-up table.

5. The method according to claim 1 , further comprising performing a cross domain check to verify the generalized macro timing abstract for the specific timing context based on the generalized macro timing abstract including a launch latch that sends data and a capture latch that receives data from the launch latch, wherein the launch latch and the capture latch are associated with two different external clock dividers.

6. The method according to claim 5 , wherein the performing the cross domain check includes comparing an effective cycle time value computed for the initial timing context with the effective cycle time value computed for the specific timing context.

7. The method according to claim 6 , further comprising computing the effective cycle time value according to:
GCD+capture_edge−launch_edge, where

GCD is a greatest common divider of clock cycles of the two different external clock dividers, launch_edge is a time of a clock edge of a clock signal driving the launch latch, and capture_edge is a time of a clock edge of a clock signal driving the capture latch.

8. A computer program product for using a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
setting up a timer;
determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value;
performing the timing analysis using the divide ratios of the one or more external clock dividers; and
generating the generalized macro timing abstract based on performing a detailed timing analysis of an associated macro using an initial timing context defined by a fastest expected clock.

9. The computer program product according to claim 8 , wherein the determining the divide ratio of each external clock divider of the one or more external clock dividers as the function of another value includes determining the divide ratio according to a name of a timing signal corresponding with each external clock divider when the timing analysis is a hierarchical timing analysis involving more than one hierarchical level of a design of the integrated circuit.

10. The computer program product according to claim 8 , wherein the determining the divide ratio of each external clock divider of the one or more external clock dividers as the function of another value includes determining the divide ratio based on a constraint at an input port of the generalized macro associated with each external clock divider or determining the divide ratio for the generalized macro timing abstract based on a look-up table.

11. The computer program product according to claim 8 , further comprising performing a cross domain check to verify the generalized macro timing abstract for the specific timing context based on the generalized macro timing abstract including a launch latch that sends data and a capture latch that receives data from the launch latch, wherein the launch latch and the capture latch are associated with two different external clock dividers, and wherein the performing the cross domain check includes comparing an effective cycle time value computed for the initial timing context with the effective cycle time value computed for the specific timing context, and computing the effective cycle time value according to:
GCD+capture_ ri sin g _edge−launch_ ri sin g _edge, where

GCD is a greatest common divider of clock cycles of the two different external clock dividers, launch_rising_edge is a time of a rising edge of a clock signal driving the launch latch, and capture_rising_edge is a time of a rising edge of a clock signal driving the capture latch.

Assignees

• IBM

Inventors

• Abdul Naiju K
• Basile Jennifer E
• Gupta Hemlata
• Kalafala Kerim
• Leitzen Jeremy J
• Shuma Stephen G
• Verma Manish
• Warnock James D
• Wood Michael H

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/396

  Clock trees · CPC title

• G06F2217/62

  Physics · mapped topic

• G06F2217/84

  Physics · mapped topic