Initializing scannable and non-scannable latches from a common clock buffer

Patent metadata

Field	Value
Publication number	US-9762212-B1
Application number	US-201615245896-A
Country	US
Kind code	B1
Filing date	Aug 24, 2016
Priority date	Aug 24, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

First claim

What is claimed:

1. A system for initializing scannable and non-scannable latches from a common clock buffer, the system comprising:
a processor, coupled to a memory, configured to perform a method, the method comprising:
receiving a clock signal into a local clock buffer;
receiving, at each clock signal, a set of control signals including a hold control signal, a scan enable control signal, and a non-scannable latch force control signal;
responsive to receiving a low input from the hold control signal and the scan enable control signal, outputting a high signal from a functional clock port on the local clock buffer on a next clock cycle;
responsive to receiving a high input from the scan enable control signal and a low input from the hold control signal, outputting a high slave latch scan clock signal on the next clock cycle;
responsive to receiving a high input from the hold control signal and the scan enable control signal, outputting a high master latch scan clock signal on the next clock cycle; and
responsive to receiving a high input from the non-scannable latch force control signal, outputting a low master latch scan clock signal on a current clock cycle.

2. The system of claim 1 , wherein the local clock buffer is coupled to one or more scannable latches and at least one non-scannable latch.

3. The system of claim 1 , wherein the hold control signal comprises:
a non-scannable latch hold control signal and a scannable latch hold control signal passing through one or more digital logic gates.

4. The system of claim 3 , wherein the one or more digital logic gates is a two input AND logic gate with the non-scannable latch hold control signal as a first input and the scannable latch hold control signal as a second input.

5. The system of claim 1 , wherein the non-scannable latch force control signal passes through one or more digital logic gates within the local clock buffer.

6. The system of claim 5 , wherein the one or more digital logic gates is a OR gate with the non-scannable latch force control signal as a first input and an invert of the scan enable control signal as a second input.

7. A computer program product for initializing scannable and non-scannable latches from a common clock buffer, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to cause the processor to perform a method comprising:
receiving a clock signal into a local clock buffer;
receiving, at each clock signal, a set of control signals including a hold control signal, a scan enable control signal, and a non-scannable latch force control signal;
responsive to receiving a low input from the hold control signal and the scan enable control signal, outputting a high signal from a functional clock port on the local clock buffer on a next clock cycle;
responsive to receiving a high input from the scan enable control signal and a low input from the hold control signal, outputting a high slave latch scan clock signal on the next clock cycle;
responsive to receiving a high input from the hold control signal and the scan enable control signal, outputting a high master latch scan clock signal on the next clock cycle; and
responsive to receiving a high input from the non-scannable latch force control signal, outputting a low master latch scan clock signal on a current clock cycle.

8. The computer program product of claim 7 , wherein the local clock buffer is coupled to one or more scannable latches and at least one non-scannable latch.

9. The computer program product of claim 7 , wherein the hold control signal comprises:
a non-scannable latch hold control signal and a scannable latch hold control signal passing through one or more digital logic gates.

10. The computer program product of claim 9 , wherein the one or more digital logic gates is a two input AND logic gate with the non-scannable latch hold control signal as a first input and the scannable latch hold control signal as a second input.

11. The computer program product of claim 7 , wherein the non-scannable latch force control signal passes through one or more digital logic gates within the local clock buffer.

12. The computer program product of claim 11 , wherein the one or more digital logic gates is a OR gate with the non-scannable latch force control signal as a first input and an invert of the scan enable control signal as a second input.

13. The computer program product of claim 8 , wherein the one or more scannable latches are master-slave latches comprising a one port master latch and a two port slave latch.

Assignees

• IBM

Inventors

• Huott William V
• Nigaglioni Ricardo H
• Schmidt Hagen
• Warnock James D

Classifications

• G06F13/4243

  with synchronous protocol · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F13/1673

  using buffers · CPC title