Programmable integrated circuit standard cell

Patent metadata

Field	Value
Publication number	US-10062709-B2
Application number	US-201615275514-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Sep 26, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.

First claim

What is claimed is:

1. A non-transitory computer-readable storage medium having at least one design file located thereon, the at least one design file containing a standard cell design, the standard cell design partially personalized by local wiring and for use within an integrated circuit (IC), the standard cell design comprising:
a set of transistors, each transistor of the set of transistors having a fixed size and a fixed position within an established perimeter of the standard cell, the set of transistors at least partially interconnected to a set of local nodes by the local wiring located on a first local wiring layer;
a set of customization ports arranged on a first global wiring layer and electrically connected to the set of local nodes;
a set of blockage shapes arranged to identify, on the first global wiring layer, a set of areas reserved for personalization wiring;
a fixed number of input/output (I/O) connection ports electrically connected to the set of local nodes, and
a set of parameters representing timing characteristics of the standard cell;
the personalization wiring, configured to complete the personalization of the standard cell by electrically interconnecting, on the first global wiring layer, at least some customization ports of the set of customization ports.

2. The storage medium of claim 1 , wherein the first local wiring layer is located between the transistors and the first global wiring layer.

3. The storage medium of claim 1 , further comprising a second local wiring layer and a second global wiring layer.

4. The storage medium of claim 1 , wherein the set of transistors includes at least one N-channel field-effect transistor (NFET) and at least one P-channel field-effect transistor (PFET).

5. The storage medium of claim 1 , wherein the set of blockage shapes are represented within at least one design file associated with the standard cell.

6. The storage medium of claim 1 , wherein the set of transistors, the local wiring, the established perimeter of the standard cell, the set of local nodes, the set of customization ports, the fixed number of I/O connection ports and the set of parameters representing timing characteristics are represented within at least one design file associated with the standard cell.

7. The storage medium of claim 1 , wherein the personalization wiring includes a plurality of arrangements, the plurality of arrangements, when implemented, configuring the standard cell to perform a plurality of unique logic functions.

8. The storage medium of claim 7 , wherein at least two of the plurality of unique logic functions are symmetrical.

9. A computer-implemented method of integrating and personalizing, within an integrated circuit (IC) design, by using a set of Electronic Design Automation (EDA) tools, a standard cell partially personalized by local wiring that electrically interconnects a set of local nodes, the standard cell including, on a global wiring layer, a set of areas reserved for personalization wiring and a set of customization ports, the customization ports electrically connected to the set of local nodes, the method comprising:
instantiating the partially personalized standard cell within the IC design;
assigning, to the partially personalized standard cell, a function property corresponding to a logical function of a set of logical functions;
connecting, with personalization wiring, and by using an EDA tool from the set of EDA tools, in accordance with the function property, at least some customization ports of the set of customization ports arranged on the global wiring layer;
connecting, based on a set of blockage shapes defined within the standard cell and by using an IC wiring routing program of the set of EDA tools, signal wires to input/output (I/O) connection ports of the standard cell; and
completing, by using an EDA tool from the set of EDA tools, post processing and checking of the IC design.

10. The method of claim 9 , wherein the instantiating of the partially personalized standard cell includes using an EDA tool that is selected from the group consisting of: a schematic capture tool and a logic synthesis tool.

11. The method of claim 9 , wherein the assigning a function property to the partially personalized standard cell includes using an EDA tool that is selected from the group consisting of: a schematic capture tool and a logic synthesis tool.

12. The method of claim 9 , wherein the connecting, in accordance with the function property, at least some of the customization ports, includes using a logic synthesis tool.

13. The method of claim 9 , wherein the connecting, using an IC wiring routing program, of I/O connection ports of the standard cell includes using a netlist generated from an EDA tool that is selected from the group consisting of: a schematic capture tool and a logic synthesis tool.

14. The method of claim 9 , further comprising designing and characterizing, prior to the instantiating of the partially personalized standard cell, a personalization corresponding to each logic function of the set of logic functions.

15. The method of claim 14 , wherein characterizing a personalization includes generating a set of parameters representing timing characteristics of the standard cell.

16. A computer-implemented method of implementing, by using a set of Electronic Design Automation (EDA) tools, an engineering change order (ECO) for an integrated circuit (IC) design, the IC design having an instantiated standard cell that is partially personalized by local wiring electrically interconnecting a set of local nodes, the standard cell including, on a global wiring layer, a first set of personalization wiring and a set of customization ports, the customization ports electrically connected to the set of local nodes, the first set of personalization wiring arranged to complete the personalization of the standard cell according to a first function property by electrically interconnecting a first subset of customization ports of the set of customization ports, the method comprising:
identifying the instantiated standard cell to be converted from a first logical function to a second logical function;
replacing, by using an EDA tool from the set of EDA tools, the first function property associated with the instantiated standard cell with a second function property;
removing, from the global wiring layer of the instantiated standard cell, the first set of personalization wiring corresponding to the first function property;
adding, according to a set of blockage shapes defined within the instantiated standard cell, to the global wiring layer of the instantiated standard cell, a second set of personalization wiring corresponding to the second function property, the second set personalization wiring arranged to complete the personalization of the standard cell according to the second function property by electrically interconnecting a second subset of customization ports of the set of customization ports; and
completing, by using an EDA tool from the set of EDA tools, post processing and checking of the IC design.

17. The method of claim 16 , further comprising replacing, by using an IC wiring routing program of the set of EDA tools, a first set of signal wires connected to input/output (I/O) connection ports of the standard cell with a second set of signal wires connected to I/O connection ports of the standard cell.

18. The method of claim 16 , wherein the adding a second set of personalization wiring corresponding to the second function property to the global wiring layer of the insta

Assignees

• IBM

Inventors

• Datta Ayan
• Shukla Ankur
• Warnock James D

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L2027/11875

  Electricity · mapped topic

• G06F17/5054

  Physics · mapped topic