Adjusting scan connections based on scan control locations

Patent metadata

Field	Value
Publication number	US-9934348-B2
Application number	US-201514973764-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

First claim

What is claimed is:

1. A method comprising:
receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections;
dividing the plurality of latches into one or more clusters;
determining a number of scan controls for each cluster;
placing the determined scan controls in selected locations, wherein the selected location for each scan control corresponds to a location where the cumulative distance from the scan control to each latch is minimized; and
adjusting the scan connections based on the scan control location; and
altering an integrated circuit corresponding to the circuit design according to the adjusted scan connections.

2. The method of claim 1 , wherein dividing the plurality of latches into clusters comprises partitioning the latches into clusters based on the physical latch locations.

3. The method of claim 1 , wherein determining a number of scan controls required per cluster comprises:
determining a number of latches in each cluster and the distance between the latches in each cluster;
calculating a number of latches a scan control can support within each cluster; and
determining the number of scan controls capable of supporting each cluster.

4. The method of claim 1 , wherein placing the determined scan controls in selected locations comprises:
determining a location at which a cumulative distance from the scan control to each latch is minimized; and
placing the scan control at the determined location.

5. The method of claim 1 , wherein adjusting the scan connections based on the scan control location comprises:
determining a shortest path that connects the latches in the cluster and the scan control in the cluster; and
adjusting the scan connections to match the determined shortest path.

6. The method of claim 1 , wherein a scan control comprises:
any combinational gate that can be used to execute a scan operation; and
any sequential non-scan gate that can be used to execute a scan operation or a non-scan operation.

7. The method of claim 1 , wherein adjusting the scan connections comprises reordering occurrences of the existing scan connections.

8. A computer program product comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising instructions to:
receive a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections;
divide the plurality of latches into one or more clusters;
determine a number of scan controls for each cluster;
place the determined scan controls in selected locations, wherein the selected location for each scan control corresponds to a location where the cumulative distance from the scan control to each latch is minimized;
adjust the scan connections based on the scan control location; and
alter an integrated circuit corresponding to the circuit design according to the adjusted scan connections.

9. The computer program product of claim 8 , wherein the instructions to divide the plurality of latches into clusters comprise instructions to partition the latches into clusters based on the physical latch locations.

10. The computer program product of claim 8 , wherein the instructions to determine a number of scan controls required per cluster comprise instructions to:
determine a number of latches in each cluster and the distance between the latches in each cluster;
calculate a number of latches a scan control can support within each cluster; and
determine the number of scan controls capable of supporting each cluster.

11. The computer program product of claim 8 , wherein the instructions to place the determined scan controls in selected locations comprise instructions to:
determine a location at which a cumulative distance from the scan control to each latch is minimized; and
place the scan control at the determined location.

12. The computer program product of claim 8 , wherein the instructions to adjust the scan connections based on the scan control location comprise instructions to:
determine a shortest path that connects the latches in the cluster and the scan control in the cluster; and
adjust the scan connections to match the determined shortest path.

13. The computer program product of claim 8 , wherein a scan control comprises:
any combinational gate that can be used to execute a scan operation; and
any sequential non-scan gate that can be used to execute a scan operation or a non-scan operation.

14. The computer program product of claim 8 , wherein the instructions to adjust the scan connections comprise instructions to reorder occurrences of the existing scan connections.

15. A computer system comprising:
one or more computer processors;
one or more computer-readable storage media;
program instructions stored on the computer-readable storage media for execution by at least one of the one or more processors, the program instructions comprising instructions to:
receive a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections;
divide the plurality of latches into one or more clusters;
determine a number of scan controls for each cluster;
place the determined scan controls in selected locations, wherein the selected location for each scan control corresponds to a location where a cumulative distance from the scan control to each latch is minimized; and
adjust the scan connections based on the scan control location; and
alter an integrated circuit corresponding to the circuit design according to the adjusted scan connections.

16. The computer system of claim 15 , wherein the instructions to divide the plurality of latches into clusters comprise instructions to partition the latches into clusters based on the physical latch locations.

17. The computer system of claim 15 , wherein the instructions to determine a number of scan controls required per cluster comprise instructions to:
determine a number of latches in each cluster and the distance between the latches in each cluster;
calculate a number of latches a scan control can support within each cluster; and
determine the number of scan controls capable of supporting each cluster.

18. The computer system of claim 15 , wherein the instructions to place the determined scan controls in selected locations comprise instructions to:
determine a location at which a cumulative distance from the scan control to each latch is minimized; and
place the scan control at the determined location.

19. The computer system of claim 15 , wherein the instructions to adjust the scan connections based on the scan control location comprise instructions to:
determine a shortest path that connects the latches in the cluster and the scan control in the cluster; and
adjust the scan connections to match the determined shortest path.

20. The computer system of claim 15 , wherein a scan control comprises:
any combinational gate that can be used to execute a scan operation; and
any sequential non-scan gate that can be used to execute a scan operation or a non-scan operation.

Assignees

• IBM

Inventors

• Gopalakrishnasetty Raghu G
• Kagliwal Ankit N
• Rangarajan Sridhar H
• Warnock James D

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title

• G06F17/5072 Primary

  Physics · mapped topic