Method of forming multiple-Vt FETS for CMOS circuit applications
US-12588270-B2 · Mar 24, 2026 · US
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Wang Wei-E patents
Wang Wei-E is listed as an inventor on 52 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wang Wei-E |
| Total patents | 52 |
| First publication | Jun 23, 2015 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Method of forming multiple-vt fets for cmos circuit applications
US-2023361194-A1 · Nov 9, 2023 · US
Method of forming multiple-Vt FETS for CMOS circuit applications
US-11749739-B2 · Sep 5, 2023 · US
Method of forming a thermal shield in a monolithic 3-d integrated circuit
US-11605574-B2 · Mar 14, 2023 · US
Method of forming multi-threshold voltage devices and devices so formed
US-11476121-B2 · Oct 18, 2022 · US
Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
US-11404405-B2 · Aug 2, 2022 · US
Method of forming multiple-vt fets for cmos circuit applications
US-2021376109-A1 · Dec 2, 2021 · US
Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
US-11189600-B2 · Nov 30, 2021 · US
Method of forming isolation dielectrics for stacked field effect transistors (FETs)
US-11158738-B2 · Oct 26, 2021 · US
Method of forming multiple-Vt FETs for CMOS circuit applications
US-11088258-B2 · Aug 10, 2021 · US
Recent patents
Latest publications not already listed above.
Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material
US-11081590-B2 · Aug 3, 2021 · US
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
US-11069576-B2 · Jul 20, 2021 · US
Method of forming a thermal shield in a monolithic 3-d integrated circuit
US-2021183729-A1 · Jun 17, 2021 · US
Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
US-2021183814-A1 · Jun 17, 2021 · US
Method of forming a thermal shield in a monolithic 3-D integrated circuit
US-10971420-B2 · Apr 6, 2021 · US
Method of forming isolation dielectrics for stacked field effect transistors (fets)
US-2020403097-A1 · Dec 24, 2020 · US
Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
US-2020381414-A1 · Dec 3, 2020 · US
Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
US-10854591-B2 · Dec 1, 2020 · US
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
US-2020357700-A1 · Nov 12, 2020 · US
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
US-10770353-B2 · Sep 8, 2020 · US
Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same
US-10727297-B2 · Jul 28, 2020 · US
Method of forming a thermal shield in a monolithic 3-d integrated circuit
US-2020203247-A1 · Jun 25, 2020 · US
Method of forming multiple-vt fets for cmos circuit applications
US-2020194569-A1 · Jun 18, 2020 · US
Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed
US-10586738-B2 · Mar 10, 2020 · US
Method of forming crystalline oxides on iii-v materials
US-2020035838-A1 · Jan 30, 2020 · US
Method of forming multi-threshold voltage devices and devices so formed
US-2019385856-A1 · Dec 19, 2019 · US
Method of forming crystalline oxides on III-V materials
US-10475930-B2 · Nov 12, 2019 · US
Method of forming multi-threshold voltage devices and devices so formed
US-10446400-B2 · Oct 15, 2019 · US
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
US-2019148237-A1 · May 16, 2019 · US
Method of providing source and drain doping for cmos architecture including finfet and semiconductor devices so formed
US-2019131182-A1 · May 2, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Samsung Electronics Co Ltd | 51 |
| Wang Wei-E | 4 |
| Rodder Mark S | 3 |
| Univ Texas | 3 |
| Bowen Robert C | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 27 |
| H10D84/83 | 19 |
| H10D84/85 | 19 |
| H10D64/01318 | 18 |
| H01L21/28088 | 18 |