Method of forming multi-threshold voltage devices and devices so formed

Patent metadata

Field	Value
Publication number	US-11476121-B2
Application number	US-201916551028-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Oct 20, 2017
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

First claim

We claim:

1. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:
providing a silicate layer, the silicate layer including at least one of LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AISiOx, TiSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx, where Ox indicates an oxide with a varying stoichiometry;
providing a high dielectric constant layer on the silicate layer; and
performing a low temperature anneal after the step of providing the silicate layer,
wherein a first portion of the plurality of components has a first maximum thickness of the silicate layer, a second portion of the plurality of components has a second maximum thickness of the silicate layer, and a third portion of the plurality of components has a third maximum thickness of the silicate layer, and
wherein the first maximum thickness, the second maximum thickness and the third maximum thickness are different from one another.

2. The method of claim 1 , further comprising:
providing a work function metal layer on the high dielectric constant layer.

3. The method of claim 1 , further comprising:
providing a reactive metal layer on at least a portion of the high dielectric constant layer.

4. The method of claim 3 , wherein the reactive metal layer includes at least one of Ti, Zr, Hf and La.

5. The method of claim 1 , wherein the low temperature anneal has an anneal temperature of not more than six hundred degrees Celsius.

6. The method of claim 1 , wherein the high dielectric constant layer has a dielectric constant greater than a silicon dioxide dielectric constant.

7. The method of claim 6 , wherein the high dielectric constant layer includes hafnium oxide.

8. The method of claim 1 , further comprising:
providing an interfacial oxide layer before the step of providing the silicate layer.

9. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:
providing a silicate layer on a substrate, wherein a first portion of the plurality of components has a first maximum thickness of the silicate layer, a second portion of the plurality of components has a second maximum thickness of the silicate layer, and a third portion of the plurality of components has a third maximum thickness of the silicate layer
providing a high dielectric constant layer on the silicate layer; and
performing a low temperature anneal after the step of providing the high dielectric constant layer;
wherein the first maximum thickness, the second maximum thickness and the third maximum thickness are different from one another.

10. The method of claim 9 , wherein the first thickness and the second thickness are each less than two nanometers.

11. The method of claim 10 , wherein the first thickness and the second thickness are each not more than one nanometer and at least 0.1 nanometer.

12. The method of claim 9 , wherein each of the first silicate layer and the second silicate layer includes at least one of LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx, where Ox indicates an oxide with a varying stoichiometry.

13. The method of claim 9 , the step of providing the silicate layer further comprising:
forming a first silicate layer on the first portion and the second portion of the plurality of components;
forming a second silicate layer on the second portion of the plurality of components;
forming a third silicate layer on the first portion, the second portion and the third portion of the plurality of components.

14. The method of claim 9 , further comprising:
providing a reactive metal layer before the step of performing the low temperature anneal.

15. The method of claim 14 , wherein the reactive metal layer includes at least one of Ti, Zr, Hf and La and has a reactive metal layer thickness of not more than four nanometers.

16. The method of claim 14 , the step of providing the reactive metal layer including:
depositing a layer including a desired reactive metal.

17. The method of claim 9 , wherein the low temperature anneal has an anneal temperature of not more than six hundred degrees Celsius.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark S
• Obradovic Borna J

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01332 Primary

  Making the insulator · CPC title

• H01L29/517

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L21/28158 Primary

  Electricity · mapped topic