Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10727297-B2
Application number	US-201615348916-A
Country	US
Kind code	B2
Filing date	Nov 10, 2016
Priority date	Sep 12, 2016
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A complimentary metal-oxide-semiconductor (CMOS) circuit including: a substrate; and a plurality of field-effect transistors on the substrate. Each of the field-effect transistors includes: a plurality of contacts; a source connected to one of the contacts; a drain connected to another one of the contacts; a gate; and a spacer between the gate and the contacts. The spacer of one of the field-effect transistors has a larger airgap than the spacer of another one of the field-effect transistors.

First claim

What is claimed is:

1. A complimentary metal-oxide-semiconductor (CMOS) circuit comprising:
a substrate; and
a plurality of field-effect transistors on the substrate, each of the field-effect transistors comprising:
a plurality of contacts;
a source connected to one of the contacts;
a drain connected to another one of the contacts;
a gate; and
a spacer between the gate and the contacts,

wherein the spacer of a first one of the field-effect transistors has a larger airgap than the spacer of a second one of the field-effect transistors, and
wherein the spacers of both the first and second field-effect transistors have a same height from a bottom surface of spacers to an upper surface thereof in a direction normal to the substrate.

2. The CMOS circuit of claim 1 , wherein the spacer of the first field-effect transistor has an overall density that is less than the spacer of the second field-effect transistor.

3. The CMOS circuit of claim 1 , wherein the gate of each of the field-effect transistors comprises a metal gate and a high-k dielectric material at a bottom of and around a periphery of the metal gate, each of the metal gates comprising the same material, and
wherein the effective work function of the metal gate of the one of the field-effect transistors is different from the effective work function of the metal gate of the other one of the field-effect transistors.

4. The CMOS circuit of claim 1 , wherein the spacer of the second field-effect transistor does not have the airgap.

5. The CMOS circuit of claim 4 , wherein the gate of each of the field-effect transistors comprises a same work function metal.

6. A method of manufacturing a complimentary metal-oxide-semiconductor (CMOS) circuit, the method comprising:
forming a plurality of field-effect transistors on a substrate, each of the field-effect transistors comprises a plurality of contacts, a source connected to one of the contacts, a drain connected to another one of the contacts, a gate, and a first spacer between the gate and the contacts;
etching the first spacer from only some of the field-effect transistors; and
forming a second spacer in the field-effect transistors from which the first spacer was etched and at where the first spacer was etched, the second spacer comprising an airgap.

7. The method of claim 6 , wherein, after the etching of the first spacer and before the forming of the second spacer, a first group of the field-effect transistors comprises the first spacer and a second group of the field-effect transistors has an unoccupied gap between the gate and the contacts.

8. The method of claim 7 , wherein, after the forming of the second spacer, the second group of the field-effect transistors has a different threshold voltage than the first group of the field-effect transistors.

9. The method of claim 6 , wherein the forming of the field-effect transistors comprises planarizing the gate.

10. The method of claim 9 , wherein the etching of the first spacer occurs directly after the planarizing the gate.

11. The method of claim 6 , wherein the forming of the second spacer comprises a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, a low-pressure chemical vapor deposition process, a reduced-pressure chemical vapor deposition process, or an atomic layer deposition process.

12. The method of claim 11 , wherein the forming of the second spacer further comprises depositing tetraethyl orthosilicate in an oxygen and/or ozone environment.

13. The method of claim 11 , wherein the forming of the second spacer further comprises depositing silicon nitride, silicon oxycarbonitride, or silicon-boron-carbide-nitride in a hydrogen or reducing environment.

14. The method of claim 6 , wherein the forming of the field-effect transistors comprises a replacement metal gate process.

15. The method of claim 6 , wherein the substrate has a crystalline orientation of (100) or (110).

16. The method of claim 6 , wherein the substrate is a bulk substrate or a silicon on insulator substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Hong Joon Goo

Classifications

• H10D84/8316

  the IGFETs characterised by having gate sidewall spacers specially adapted for integration · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/679

  comprising air gaps · CPC title

• H10D84/0147 Primary

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title