Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed

Patent metadata

Field	Value
Publication number	US-11069576-B2
Application number	US-202016942762-A
Country	US
Kind code	B2
Filing date	Jul 29, 2020
Priority date	Nov 16, 2017
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.

First claim

I claim:

1. A semiconductor device comprising:
a substrate; and
a plurality of components on the substrate, each of the plurality of components including a source, a drain, a channel and a gate structure, the channel being between the source and drain, the gate structure adjacent to the channel region, the gate structure for a first portion of the plurality of components including a first dipole combination, the gate structure for a second portion of the plurality of components including a second dipole combination different from the first dipole combination, the first dipole combination including a first dipole layer and a first high dielectric constant layer on the first dipole layer, the second dipole combination including a second dipole layer and a second high dielectric constant layer on the second dipole layer, the gate structure further including a work function metal layer and a contact metal layer, the second dipole combination being different from the first dipole combination, the first dipole layer and the second dipole layer being selected from lanthanum oxide, lanthanum silicon oxide, aluminum oxide and yttrium oxide, and the first high dielectric constant layer and the second high dielectric constant layer including hafnium oxide, wherein the gate structure for a third portion of the plurality of components includes a third dipole combination different from the first and second dipole combinations, the third dipole combination including a third dipole layer and a third high dielectric constant layer on the third dipole layer, the third dipole combination being different from the first dipole combination and the second dipole combination.

2. The semiconductor device of claim 1 , wherein the third dipole layer is selected from lanthanum oxide, lanthanum silicon oxide, aluminum oxide and yttrium oxide.

3. The semiconductor device of claim 1 wherein the first dipole layer is selected from Al 2 O 3 and Y 2 O 3 and the first high dielectric constant layer includes HfO 2 .

4. The semiconductor device of claim 1 wherein the second dipole layer is selected from Al 2 O 3 and Y 2 O 3 and the second high dielectric constant layer includes HfO 2 .

5. The semiconductor device of claim 1 , wherein the first portion of the plurality of components has a first band displacement for the first high dielectric constant layer and the second portion of the plurality of components has a second band displacement for the second high dielectric constant layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D48/01

  Manufacture or treatment · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/014

  the gate conductors having different materials or different implants · CPC title