Method of forming multi-threshold voltage devices and devices so formed

Patent metadata

Field	Value
Publication number	US-10446400-B2
Application number	US-201815898420-A
Country	US
Kind code	B2
Filing date	Feb 16, 2018
Priority date	Oct 20, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

First claim

We claim:

1. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:
providing a silicate layer, the silicate layer including at least one of LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx;
providing a high dielectric constant layer on the silicate layer;
providing a work function metal layer on the high dielectric constant layer;
performing a low temperature anneal after the step of providing the high dielectric constant layer; and
providing a contact metal layer on the work function metal layer.

2. The method of claim 1 wherein the high dielectric constant layer has a dielectric constant greater than a silicon dioxide dielectric constant.

3. The method of claim 1 further comprising:
providing an interfacial oxide layer before the step of providing the silicate layer.

4. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising
providing a silicate layer, wherein a first portion of the plurality of components has a first thickness of the silicate layer and wherein a second portion of the plurality of components has a second thickness of the silicate layer, the second thickness being different from the first thickness, the step of providing the silicate layer further comprising
depositing a first silicate layer on at least the first portion and the second portion of the plurality of components;
removing at least a portion of the first silicate layer from the first portion of the plurality of components; and
providing a second silicate layer on the first portion and the second portion of the plurality of components;

providing a high dielectric constant layer on the silicate layer;
providing a work function metal layer on the high dielectric constant layer;
performing a low temperature anneal after the step of providing the high dielectric constant layer; and
providing a contact metal layer on the work function metal layer.

5. The method of claim 4 wherein the first thickness and the second thickness are each less than two nanometers.

6. The method of claim 5 wherein the first thickness and the second thickness are each not more than one nanometer and at least 0.1 nanometer.

7. The method of claim 4 wherein each of the first silicate layer and the second silicate layer includes at least one of LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx.

8. The method of claim 4 wherein a third portion of the plurality of components has a third thickness of the silicate layer, the third thickness being different from the first thickness and different from the second thickness, the step of providing the silicate layer further comprising:
depositing a third silicate layer on at least the first portion, the second portion and the third portion of the plurality of components;
removing at least a portion of the third silicon layer from the first portion and the second portion of the plurality of components;
wherein the step of depositing the first silicate layer includes depositing the first silicate layer on the third portion of the plurality of components;
wherein the step of removing the at least a portion of the first silicate layer from the first portion of the plurality of components is performed such that the first silicate layer remains on the third portion of the plurality of components; and
wherein the step of providing a second silicate layer on the first portion and the second portion of the plurality of components also provides the second silicate layer on the third portion of the plurality of components.

9. The method of claim 4 further comprising:
providing a reactive metal layer on the work function layer before the step of providing the contact metal layer and before the step of performing the low temperature anneal, the step of performing the low temperature anneal being performed before the step of providing the contact metal layer; and
removing the reactive metal layer after the step of performing the low temperature anneal and before the step of providing the contact metal layer.

10. The method of claim 9 wherein the reactive metal layer includes at least one of Si, Ti, Zr, Hf and La and has a reactive metal layer thickness of not more than four nanometers.

11. The method of claim 9 wherein the reactive metal layer resides on only a portion of the plurality of components during the low temperature anneal, the step of providing the reactive metal layer including:
depositing a layer including a desired reactive metal; and
removing a portion of the layer such that the reactive metal layer remains on the portion of the plurality of components.

12. The method of claim 4 wherein the work function metal layer includes at least one of TiN, TaN, TiSiN, TiTaN, WN and TiTaSiN and has a work function metal thickness of not more than three nanometers.

13. The method of claim 4 wherein the low temperature anneal has an anneal temperature of not more than six hundred degrees Celsius.

14. The method of claim 13 wherein the high dielectric constant material includes hafnium oxide.

15. A method for providing a plurality of transistors on a semiconductor device, the method comprising:
providing a source and a drain for each of the plurality of transistors, a channel for each of the plurality of transistors, being between the source and the drain;
providing a gate structure on the channel for each of the plurality of transistors, the step of providing the gate structure comprising
providing an interfacial oxide layer on at least the channel;
providing a silicate layer on the interfacial oxide layer, a first portion of the plurality of transistors having a first thickness of the silicate layer, a second portion of the plurality of transistors having a second thickness of the silicate layer, the second thickness being different from the first thickness, the step of providing the silicate layer including
depositing a first silicate layer on the first portion and the second portion of the plurality of structures;
removing at least a portion of the first silicate layer from the first portion of the plurality of structures; and
providing a second silicate layer on the first portion and the second portion of the plurality of structures, each of the first silicate layer and the second silicate layer including at least one of LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx;

providing a high dielectric constant layer on the silicate layer;
providing a work function metal layer on the high dielectric constant layer, the work function metal layer including at least one of TiN, TaN, TiSiN, TiTaN, WN and TiTaSiN and having a work function metal thickness of not more than three nanometers;
providing a reactive metal layer on at least a portion of the work function metal layer, the reactive metal layer including at least one of Si, Ti, Zr, Hf and La;
performing a low temperature anneal after the step of providing the reactive metal layer, the low temperature anneal having an anneal temperature of at least two hundred degrees Celsius and not more than six hundred degrees Celsius;
removing the reactive metal layer after the step of performing the low temperature anneal;
providing a contact metal layer on the work function metal layer after the step of removing the reactive metal layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark S
• Obradovic Borna J

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01332 Primary

  Making the insulator · CPC title

• H01L29/4966

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic

• H01L21/28088

  Electricity · mapped topic