Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed

Patent metadata

Field	Value
Publication number	US-10770353-B2
Application number	US-201815898421-A
Country	US
Kind code	B2
Filing date	Feb 16, 2018
Priority date	Nov 16, 2017
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.

First claim

I claim:

1. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:
providing a first dipole combination on a first portion of the plurality of components, the first dipole combination including a first dipole layer and a first high dielectric constant layer on the first dipole layer, the providing the first dipole combination further including
providing a masking layer on the second portion of the plurality of components;
depositing a first layer on at least the first portion and the second portion of the plurality of components, a first portion of the first layer on the first portion of the plurality of components forming the first dipole layer;
depositing an additional layer on the at least the first portion and the second portion of the plurality of components, a first portion of the additional layer on the first portion of the plurality of components forming the first high dielectric constant layer;
removing a second portion of the first layer and a second portion of the additional layer from the second portion of the plurality of components;

providing a second dipole combination on a second portion of the plurality of components, the second dipole combination including a second dipole layer and a second high dielectric constant layer on the second dipole layer, the first dipole combination being different from the second dipole combination;
providing at least one work function metal layer on the first dipole combination and the second dipole combination;
performing a low temperature anneal after the providing the at least one work function metal layer; and
providing a contact metal layer on the work function metal layer.

2. The method of claim 1 wherein the providing the at least one work function metal layer further includes:
providing a first work function metal layer on the first dipole combination; and
providing a second work function metal layer on the second dipole combination.

3. The method of claim 2 wherein the providing the first work function metal layer is performed before the second dipole combination is provided.

4. The method of claim 1 wherein the providing the second dipole combination further includes:
providing an additional masking layer on the first dipole combination;
depositing a second layer on at least the first portion and the second portion of the plurality of components, a first portion of the second layer on the second portion of the plurality of components forming the second dipole layer;
depositing a second additional layer on the at least the first portion and the second portion of the plurality of components, a first portion of the second additional layer on the second portion of the plurality of components forming the second high dielectric constant layer;
removing a second portion of the second layer and a second portion of the second additional layer from the first portion of the plurality of components.

5. The method of claim 1 wherein the first dipole combination has a first thickness and the second dipole combination has a second thickness, the first thickness and the second thickness are each less than two nanometers.

6. The method of claim 5 wherein the at least one work function metal layer is at least one nanometer and not more than three nanometers thick.

7. The method of claim 1 wherein the first dipole layer, the second dipole layer and the third dipole layer are each selected from Lu 2 O 3 , LuSiOx, Y 2 O 3 , YSiOx, La 2 O 3 , LaSiOx, BaO, BaSiOx, SrO, SrSiOx, Al 2 O 3 , AlSiOx, TiO 2 , TiSiOx, HfO 2 , HfSiOx, ZrO 2 , ZrSiOx, Ta 2 O 5 , TaSiOx, ScO, ScSiOx, MgO, and MgSiOx and wherein the first high dielectric constant layer, the second high dielectric constant layer and the third dielectric constant layer are selected from HfO 2 , ZrO 2 , HfSiOx, HfZrOx and ZrALOx.

8. The method of claim 1 wherein the low temperature anneal has an anneal temperature of not more than six hundred degrees Celsius.

9. The method of claim 8 wherein the anneal temperature is at least three hundred degrees Celsius and not more than four hundred degrees Celsius.

10. The method of claim 1 wherein the high dielectric constant layer has a dielectric constant greater than a silicon dioxide dielectric constant.

11. The method of claim 1 wherein the at least one work function metal layer includes at least one of TiN, TaN, TiSiN, TiTaN and TiTaSiN.

12. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:
providing a first dipole combination on a first portion of the plurality of components, the first dipole combination including a first dipole layer and a first high dielectric constant layer on the first dipole layer;
providing a second dipole combination on a second portion of the plurality of components, the second dipole combination including a second dipole layer and a second high dielectric constant layer on the second dipole layer, the first dipole combination being different from the second dipole combination;
providing a third dipole combination on a third portion of the plurality of components, the third dipole combination including a third dipole layer and a third high dielectric constant layer on the second dipole layer, the first dipole combination being different from the third dipole combination, the second dipole combination being different from the third dipole combination
providing at least one work function metal layer on the first dipole combination and the second dipole combination;
performing a low temperature anneal after the providing the at least one work function metal layer; and
providing a contact metal layer on the work function metal layer.

13. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:
providing a first dipole combination on a first portion of the plurality of components, the first dipole combination including a first dipole layer and a first high dielectric constant layer on the first dipole layer;
providing a second dipole combination on a second portion of the plurality of components, the second dipole combination including a second dipole layer and a second high dielectric constant layer on the second dipole layer, the first dipole combination being different from the second dipole combination;
providing at least one work function metal layer on the first dipole combination and the second dipole combination;
providing a reactive metal layer on the at least one work function metal layer for at least some of the plurality of components;
performing a low temperature anneal after the providing the at least one work function metal layer and after the providing the reactive metal layer;
removing the reactive metal layer after the performing the low temperature anneal; and
providing a contact metal layer on the work function metal layer after the performing the low temperature anneal and after the removing the reactive metal layer.

14. The method of claim 13 wherein the reactive metal layer includes at least one of Si, Ti, Zr, Hf and La and has a reactive metal layer thickness of not more than four nanometers.

15. A method for providing a plurality of transistors on a semiconductor device, the method comprising:
providing a source and a drain for each of the plurality of transistors, a channel for each of the plurality of transistors, being between the source and the drain;
providing a gate structure on the channel for each of the plurality of transistors, the step of providing the gate structure comprising
providing a fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D48/01

  Manufacture or treatment · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/014

  the gate conductors having different materials or different implants · CPC title