Method of forming crystalline oxides on III-V materials

US10475930B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10475930-B2
Application numberUS-201615359480-A
CountryUS
Kind codeB2
Filing dateNov 22, 2016
Priority dateAug 17, 2016
Publication dateNov 12, 2019
Grant dateNov 12, 2019

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  1. Title

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  2. Abstract

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Abstract

Official abstract text for this publication.

A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a crystalline oxide on a III-V material, the method comprising: providing a substrate; forming a III-V material comprising three elements on the substrate by epitaxy; and forming a crystalline oxide layer comprising an oxide on the III-V material, the step of forming the crystalline oxide layer including removing Ga 2 O 3 (Ga3+), removing In 2 O (In1+) and removing As 2 O 3 (As3+) to form a (3×2)-O Ga 2 O oxide in the crystalline oxide layer. 2. A method of forming a crystalline oxide on a III-V material, the method comprising: providing a substrate; forming a III-V material comprising three elements on the substrate by epitaxy; forming a crystalline oxide layer comprising an oxide on the III-V material; and removing Ga 2 O 3 (Ga3+), removing In 2 O (In1+) and removing As 2 O 3 (As3+) to form a (3×2)-O Ga 2 O oxide in the crystalline oxide layer; wherein removing Ga 2 O 3 (Ga3+), removing In 2 O (In1+), and removing As 2 O 3 (As3+) comprises annealing the substrate in atomic hydrogen at about 200° C. to about 400° C. for about 1 minute to about 10 minutes. 3. A method of forming a crystalline oxide on a III-V material, the method comprising: providing a substrate; forming a III-V material comprising three elements on the substrate by epitaxy; forming a crystalline oxide layer comprising an oxide on the III-V material; and adding Ga1+ to form a (3×2)-O oxide in the crystalline oxide layer. 4. A method of forming a crystalline oxide on a III-V material, the method comprising: providing a substrate; forming a III-V material comprising three elements on the substrate by epitaxy; and forming a crystalline oxide layer comprising an oxide on the III-V material; removing Ga 2 O 3 (Ga3+), removing In 2 O (In1+), and removing As 2 O 3 (As3+), such that Ga 2 O (Ga1+) remains in a crystalline manner to form a (3×2)-O oxide in the crystalline oxide layer. 5. A method of forming a crystalline oxide on a III-V material, the method comprising: providing a substrate; forming a III-V material comprising three elements on the substrate by epitaxy; forming a crystalline oxide layer comprising an oxide on the III-V material; and annealing the substrate in atomic hydrogen to remove Ga 2 O 3 (Ga3+) oxide from the crystalline oxide layer. 6. The method of claim 5 , wherein the annealing the substrate in atomic hydrogen comprises annealing in a range of about 200° C. to about 400° c. in a range of about 1 minute to about 10 minutes. 7. The method of claim 6 , wherein annealing the substrate in atomic hydrogen comprises annealing the substrate in atomic hydrogen or in atomic deuterium at a temperature of about 200° C. to about 400° c.

Assignees

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Classifications

  • the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

  • Deposition of epitaxial materials · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US10475930B2 cover?
A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer inclu…
Who is the assignee on this patent?
Samsung Electronics Co Ltd, Univ Texas
What technology area does this patent fall under?
Primary CPC classification H01L29/78681. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).