Method of forming multiple-Vt FETS for CMOS circuit applications

Patent metadata

Field	Value
Publication number	US-11749739-B2
Application number	US-202117396385-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Nov 16, 2017
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

First claim

What is claimed is:

1. A field-effect transistor (FET) device having a modulated Vt, the FET device comprising:
a source electrode;
a drain electrode;
a channel region between the source electrode and the drain electrode; and
a gate stack on the channel region, the gate stack comprising:
a layer combination comprising a plurality of oxygen dipoles to shift the modulated Vt in a first direction and by a first magnitude, and
a doped gate metal layer on the layer combination and to shift the modulated Vt in a second direction opposite the first direction and by a second magnitude smaller than the first magnitude.

2. The FET device of claim 1 , wherein the layer combination comprises:
an ultrathin dielectric dipole layer on the channel region; and
a high-k (HK) insulating layer on the ultrathin dielectric dipole layer,
wherein the plurality of oxygen dipoles are at an interface between the ultrathin dielectric dipole layer and the HK insulating layer.

3. The FET device of claim 2 , the ultrathin dielectric dipole layer being undoped and comprising a metal oxide or metal-containing silicate material.

4. The FET device of claim 2 , wherein:
the ultrathin dielectric dipole layer comprises at least one of Lu 2 O 3 , LuSiO x , Y 2 O 3 , MgO, MgSiO x , YSiO x , La 2 O 3 , LaSiO x , BaO, BaSiO x , SrO, SrSiO x , or a combination thereof, and
the HK insulating layer comprises HfO 2 , ZrO 2 , HfSiO x , HfZrO x , and ZrAlO x .

5. The FET device of claim 2 , wherein:
the ultrathin dielectric dipole layer comprises at least one of Al 2 O 3 , AlSiO x , TiO 2 , TiSiO x , ZrSiO x , TaO 2 , TaSiO x , ScO, ScSiO x , or a combination thereof; and
the HK insulating layer comprises HfO 2 , ZrO 2 , HfSiO x , HfZrO x , and ZrAlO x .

6. The FET device of claim 1 , wherein the layer combination has a thickness of less than 3 nm.

7. The FET device of claim 1 , wherein the doped gate metal layer comprises at least one of Al-doped TiN, Al-doped TaN, Zr-doped TiN, Zr-doped TaN, Hf-doped TiN, Hf-doped TaN, or a combination thereof.

8. The FET device of claim 1 , wherein the doped gate metal layer comprises at least one of Si-doped TiN, Si-doped TaN, LaO-doped TiN, LaO-doped TaN, SiO-doped TiN, SiO-doped TaN, ZrO-doped TiN, ZrO doped TaN, lanthanide metal-doped TiN, La-doped TaN, or a combination thereof.

9. The FET device of claim 1 , wherein the doped gate metal layer has a doping amount of greater than 0 at % to 4 at %.

10. The FET device of claim 1 , wherein the doped gate metal layer has a thickness of 1 nm to 5 nm.

11. The FET device of claim 1 , wherein:
the channel region comprises a plurality of nanosheets having a vertical spacing (VSP) therebetween of 5 nm to 15 nm, the nanosheets being interposed by an interfacial layer (IL) oxide and the gate stack.

12. A CMOS circuit comprising a first FET device and a second FET device, wherein:
the first FET device is the FET device of claim 1 , and
the second FET device comprises a second gate stack on a second channel region, the second gate stack comprising:
a second high-k (HK) insulating layer directly on the second channel region; and
a second doped gate metal layer on the HK insulating layer to shift a modulated Vt of the second FET device.

13. The CMOS circuit of claim 12 , further comprising one or more additional FET devices, each of the one or more additional FET devices having a gate stack with the same layers as that in the first FET device,
wherein the first FET device, the second FET device, and each of the one or more additional FET devices are different in voltage from each other by 50 mV to 100 mV.

14. The CMOS circuit of claim 13 , wherein two or more selected from the first FET device, the second FET device, and the one or more additional FET devices are different in voltage from each other by 60 mV to 80 mV.

15. A method of manufacturing a field-effect transistor (FET) device having a modulated Vt, the method comprising:
providing a channel region between a source electrode and a drain electrode,
forming a layer combination on the channel region, the layer combination comprising a plurality of oxygen dipoles to shift the modulated Vt in a first direction by a first magnitude, by:
depositing an ultrathin dielectric dipole layer on the channel region; and
depositing a first high-k (HK) insulating layer on the ultrathin dielectric dipole layer; and

depositing a doped gate metal layer on the HK insulating layer to shift the modulated Vt in a second direction by a second magnitude smaller than the first magnitude,
wherein the FET device is not annealed at a temperature above 500° C.

16. The method of claim 15 , wherein the ultrathin dielectric dipole layer is not driven through the HK insulating layer.

17. The method of claim 15 , wherein the ultrathin dielectric dipole layer is deposited via atomic layer deposition (ALD) at a temperature of 100° C. to 500° C.

18. The method of claim 15 , wherein the doped gate metal layer is deposited via atomic layer deposition (ALD) at a temperature of 100° C. to 500° C.

19. The method of claim 15 , wherein:
the depositing of the ultrathin dielectric dipole layer comprises depositing at least one of Lu 2 O 3 , LuSiO x , Y 2 O 3 , MgO, MgSiO x , YSiO x , La 2 O 3 , LaSiO x , BaO, BaSiO x , SrO, SrSiO x , or a combination thereof, or at least one of Al 2 O 3 , AlSiO x , TiO 2 , TiSiO x , ZrSiO x , TaO 2 , TaSiO x , ScO, ScSiO x , or a combination thereof; and
the depositing of the HK insulating layer comprises depositing one of HfO 2 , ZrO 2 , HfSiO x , HfZrO x , and ZrAlO x .

20. The method of claim 15 , wherein the depositing of the doped gate metal layer comprises depositing TaN or TiN with a dopant selected from Al, Zr, Hf, Si, La, ZrSiO x , TaO 2 , ZrO, and a lanthanide metal,
the dopant being comprised in an amount of greater than 0 at % to 4 at %.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark S

Classifications

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title