Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material

Patent metadata

Field	Value
Publication number	US-11081590-B2
Application number	US-201916591458-A
Country	US
Kind code	B2
Filing date	Oct 2, 2019
Priority date	Aug 17, 2016
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

First claim

The invention claimed is:

1. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that comprises three elements thereon, the epitaxial III-V material including In x Ga 1-x As, with x being in a range of about 0.2 to about 0.8;
a source electrode over the source region;
a drain electrode over the drain region; and
a crystalline oxide layer comprising an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material comprising the three elements, the crystalline oxide layer being free of Ga 2 O 3 (Ga3+).

2. The MOSFET of claim 1 , wherein the epitaxial III-V material comprises In 0.53 Ga 0.47 As.

3. The MOSFET of claim 1 , wherein a crystalline oxide layer on the epitaxial III-V material has a (3×1)-O reconstruction.

4. The MOSFET of claim 1 , wherein a crystalline oxide layer on the epitaxial III-V material has a (3×2)-O reconstruction.

5. The MOSFET of claim 1 , wherein the substrate comprises at least one of InP, InAlAs, and/or InGaAs, and wherein the epitaxial III-V material has a thickness in a range of about 3 nm to about 50 nm.

6. The MOSFET of claim 1 , wherein the epitaxial III-V material is formed on the substrate in a blanket manner.

7. The MOSFET of claim 1 , wherein the epitaxial III-V material is formed within a pre-patterned trench region and wherein the MOSFET further includes a dielectric material surrounding the pre-patterned trench region.

8. The MOSFET of claim 7 , wherein the dielectric material is an oxide.

Assignees

• Samsung Electronics Co Ltd
• Univ Texas

Inventors

• Wang Wei-E
• Rodder Mark S
• Wallace Robert M
• Qin Xiaoye

Classifications

• H10P14/6938

  the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

• H10P14/6349

  Deposition of epitaxial materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D62/852

  being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP · CPC title