Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10854591-B2
Application number	US-201715442592-A
Country	US
Kind code	B2
Filing date	Feb 24, 2017
Priority date	Nov 4, 2016
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

First claim

What is claimed is:

1. A semiconductor device comprising:
metal routing layers M 1 to Ma, a being an integer selected from 4 or greater, the metal routing layers stacking up from M 1 in a thickness direction;
a complementary pair of planar field-effect transistors (FETs) on metal routing layer Mb, b being smaller than a and selected from 3 or greater;
a first inter-layer dielectric layer comprising a first inter-layer dielectric material and between the metal routing layer Mb and the complementary pair of FETs,
a crystalline material layer comprising a polycrystalline material and formed on the first inter-layer dielectric material,
a second inter-layer dielectric layer comprising a second inter-layer dielectric material and between the complementary pair of FETs and metal routing layer M(b+ 1 ), and
metal vias through the second inter-layer dielectric layer,
wherein each of the FETs comprises a channel region formed of the polycrystalline material,
wherein the complementary pair of FETs are between the metal routing layer Mb and metal routing layer M(b+ 1 ),
wherein the channel region formed of the polycrystalline material is directly on the first inter-layer dielectric layer, and the polycrystalline material comprises polycrystalline silicon,
wherein the FETs are arranged in a repeater/buffer circuit consisting of one level of via or no vias,
wherein each of the FETs further comgrises source and drain electrodes comprising the polycrystalline material, a gate insulation layer on the crystalline material layer, a gate electrode on the gate insulation layer, low temperature contacts in direct contact with the source and drain electrodes and comprising Ti, Ni, Pt, and/or Co, and a gate spacer between the gate electrode and the low temperature contacts, the gate spacer comprising a nitride and in direct contact with the low temperature contacts, and
the metal vias connect the low temperature contacts with the metal routing layer M(b+ 1 ).

2. The semiconductor device of claim 1 , wherein b is 3, and M 3 comprises cobalt (Co) or ruthenium (Ru).

3. The semiconductor device of claim 2 , wherein M 1 , M 2 and M 3 each independently comprises cobalt (Co) or ruthenium (Ru).

4. The semiconductor device of claim 1 , further comprising an insulating material on metal routing layer Mb, and the complementary pair of planar FETs being on the insulating material.

5. The semiconductor device of claim 1 , wherein the polycrystalline material has a bandgap of about 1 eV or greater and a mobility of about 100 cm 2 N-sec or greater.

6. The semiconductor device of claim 1 , wherein the semiconductor device does not include a shallow trench isolation (STI) between the pair of planar FETs to isolate them from each other.

7. The semiconductor device of claim 1 , wherein the complementary pair of planar FETs are in an inverter configuration.

8. The semiconductor device of claim 1 , wherein each FET comprises a gate stack comprising non-crystalline materials.

9. The semiconductor device of claim 1 , wherein a thickness of the polycrystalline material is about 5 nm to about 15 nm.

10. A semiconductor device comprising: metal routing layers M 1 to Ma, a being an integer selected from 4 or greater, the metal routing layers stacking up from M 1 in a thickness direction;
a complementary pair of planar field-effect transistors (FETs) on metal routing layer Mb, b being smaller than a and selected from 3 or greater,
a first inter-layer dielectric layer comprising a first inter-layer dielectric material and between the metal routing layer Mb and the complementary pair of planar FETs,
a crystalline material layer comprising a polycrystalline material and formed on the first inter-layer dielectric material,
a second inter-layer dielectric layer comprising a second inter-layer dielectric material and between the complementary pair of FETs and metal routing layer M (b+1 ), and
metal vias through the second inter-layer dielectric layer,
wherein each of the FETs comprises a channel region formed of the polycrystalline material, and
wherein the complementary pair of planar FETs are between the metal routing layer Mb and metal routing layer M(b+1)
wherein each FET of the pair of planar FETs further comprises source and drain regions comprising the polycrystalline material of the channel region,
wherein each FET further comprises a pair of metal regions comprising Ti, Ni, Pt, and/or Co, and directly contacting the source and drain regions with regular salicide formation between the pair of metal regions and the source and drain regions,
wherein each FET further comprises a gate insulation layer on the crystalline material layer, a gate electrode on the gate insulation layer, and a gate spacer between the gate electrode and the pair of metal regions, the gate spacer comprising a nitride and in direct contact with the pair of metal regions,
wherein the FETs are arranged in a repeater/buffer circuit consisting of one level of via or no vias, and
wherein the metal vias connect the pair of metal regions with the metal routing layer M(b+1).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rakshit Titash
• Obradovic Borna J
• Bowen Chris
• Rodder Mark S

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6314

  of a metallic layer · CPC title