Top via on subtractively etched conductive line
US-12598970-B2 · Apr 7, 2026 · US
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Robison Robert patents
Robison Robert is listed as an inventor on 104 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Robison Robert |
| Total patents | 104 |
| First publication | Mar 12, 2020 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Conformal dielectric cap for subtractive vias
US-12568806-B2 · Mar 3, 2026 · US
Wraparound contact with reduced distance to channel
US-12432960-B2 · Sep 30, 2025 · US
Composite material phase change memory cell
US-12402546-B2 · Aug 26, 2025 · US
Stressed material within gate cut region
US-12402391-B2 · Aug 26, 2025 · US
Looped long channel field-effect transistor
US-12356685-B2 · Jul 8, 2025 · US
Self-aligned C-shaped vertical field effect transistor
US-12268030-B2 · Apr 1, 2025 · US
Single-mask alternating line deposition
US-12243819-B2 · Mar 4, 2025 · US
Producing stress in nanosheet transistor channels
US-2024213325-A1 · Jun 27, 2024 · US
Top via interconnect having a line with a reduced bottom dimension
US-11990410-B2 · May 21, 2024 · US
Recent patents
Latest publications not already listed above.
Interconnects having spacers for improved top via critical dimension and overlay tolerance
US-11961759-B2 · Apr 16, 2024 · US
Top via with damascene line and via
US-11894265-B2 · Feb 6, 2024 · US
Top via process with damascene metal
US-11869808-B2 · Jan 9, 2024 · US
Fully aligned top vias
US-11854884-B2 · Dec 26, 2023 · US
Top via with next level line selective growth
US-11823998-B2 · Nov 21, 2023 · US
Top via cut fill process for line extension reduction
US-11804406-B2 · Oct 31, 2023 · US
Conductive lines with subtractive cuts
US-11791258-B2 · Oct 17, 2023 · US
Source and drain contact cut last process to enable wrap-around-contact
US-11757012-B2 · Sep 12, 2023 · US
Composite material phase change memory cell
US-2023210026-A1 · Jun 29, 2023 · US
Conformal dielectric cap for subtractive vias
US-2023207387-A1 · Jun 29, 2023 · US
High aspect ratio vias for integrated circuits
US-11682617-B2 · Jun 20, 2023 · US
Wraparound contact with reduced distance to channel
US-2023178621-A1 · Jun 8, 2023 · US
Stepped top via for via resistance reduction
US-11670542-B2 · Jun 6, 2023 · US
Stressed material within gate cut region
US-2023139399-A1 · May 4, 2023 · US
Barrier-less prefilled via formation
US-11621189-B2 · Apr 4, 2023 · US
Looped long channel field-effect transistor
US-2023101235-A1 · Mar 30, 2023 · US
Top via process with damascene metal
US-2023094757-A1 · Mar 30, 2023 · US
Top via stack
US-11600565-B2 · Mar 7, 2023 · US
Fet with reduced parasitic capacitance
US-2023063973-A1 · Mar 2, 2023 · US
Self-aligned c-shaped vertical field effect transistor
US-2023067119-A1 · Mar 2, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 103 |
| Int Business Machines Corporation | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/42 | 55 |
| H01L23/5226 | 54 |
| H10W20/056 | 44 |
| H10W20/063 | 44 |
| H10W20/069 | 41 |