Top via process with damascene metal

Patent metadata

Field	Value
Publication number	US-11869808-B2
Application number	US-202117481362-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Sep 22, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

First claim

What is claimed is:

1. A method of forming a back end of line semiconductor wiring structure, the method comprising:
forming a plurality of first metal lines in a first dielectric material using a dual damascene process;
recessing the plurality of metal lines using a wet etching process;
depositing a second dielectric material above the plurality of first metal lines;
selectively removing a portion of the second dielectric material above at least one line of the plurality of first metal lines;
depositing an etch stop material over exposed surfaces of the first dielectric material, the second dielectric material, and the at least one line of the plurality of first metal lines;
depositing a third dielectric material over the etch stop material;
selectively removing a portion of the third dielectric material above the at least one line of the plurality of first metal lines;
selectively removing a portion of the etch stop material above the at least one line of the plurality of first metal lines; and
depositing a second metal material over the exposed surfaces of the first dielectric material, the second dielectric material, and the at least one line of the plurality of first metal lines.

2. The method of claim 1 , further comprises performing a chemical mechanical polish to remove excess portions of the second metal material to form one or more second metal lines, wherein at least one second line of the one of more second lines is above a top via composed of the second metal material on the at least one line of the plurality of first metal lines.

3. The method of claim 1 , wherein the depositing the second metal material over the exposed surfaces of the first dielectric material, the second dielectric material, and the at least one line of the plurality of first metal lines further comprises:
depositing the second metal material over the at least one line of the plurality of first metal lines in the first dielectric material using one of an electroplating process or a reflow process.

4. The method of claim 3 , wherein the depositing the second material uses the reflow process, further comprises:
depositing the second metal material using a physical vapor deposition;
heating the second metal material to melt and reflow the second metal material; and
depositing another layer of the first metal material that is different than the second metal material using electroplating over the second metal material, over exposed surfaces of the first dielectric material, and the third dielectric material.

5. The method of claim 1 , wherein the depositing the second metal material over the exposed surfaces of the first dielectric material, the second dielectric material, and the at least one line of the plurality of first metal lines further comprises:
using self-aligning processes to form a top via composed of the second metal material above the at least one line of the plurality of first metal lines and to form a second metal line over a top via, wherein the second metal line composed of the second metal material is formed after removing excess portions of the second metal material over the third dielectric material.

6. The method of claim 1 , wherein the selectively removing the portion of the etch stop material above the at least one line of the plurality of first metal lines, further comprises:
one or more portions of the etch stop material remain under remaining portions of the third dielectric material; and
one or more portions of the second dielectric material remain under the one or more portions of the etch stop material that remains after the selectively removing of the portion of the etch stop material.

Assignees

• IBM

Inventors

• Clevenger Lawrence A
• Anderson Brent
• Lanzillo Nicholas Anthony
• Penny Christopher J
• Choi Kisik
• Robison Robert

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/052

  by treatments not introducing additional elements therein · CPC title