Stressed material within gate cut region

Patent metadata

Field	Value
Publication number	US-12402391-B2
Application number	US-202117516505-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Nov 1, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

First claim

What is claimed is:

1. A semiconductor device comprising:
one or more first fins that extend from a planar top surface of a substrate within a first device region;
one or more second fins that extend from the planar top surface of the substrate within a second device region;
first shallow trench isolation (STI) within the first device region, the first STI upon the planar top surface of the substrate and upon and between respective lower portion(s) of the one or one or more first fins, the first STI comprising a first STI sidewall that faces the second device region;
second STI within the second device region, the second STI upon the planar top surface of the substrate and upon and between respective lower portion(s) of the one or one or more second fins, the second STI comprising a second STI sidewall that faces the first device region;
a first gate within the first device region, the first gate upon the first STI and upon and between respective upper portion(s) of the one or more first fins, the first gate comprising a first gate sidewall that faces the second device region;
a second gate within the second device region, the second gate upon the second STI and upon and between respective upper portion(s) of the one or more second fins, the second gate comprising a second gate sidewall that faces the first device region; and
a gate cut stressor upon the planar top surface of the substrate, upon the first STI sidewall, upon the second STI sidewall, upon the first gate sidewall, and upon the second gate sidewall, the gate cut stressor comprising a first gate cut stressor material and a second gate cut stressor material directly upon the first gate cut stressor material, wherein the second gate cut stressor material different from the first gate cut stressor material and wherein the gate cut stressor comprises an intrinsic stress that applies a tensile force to the first gate and to the second gate perpendicular to the first fins and to the second fins.

2. The semiconductor device of claim 1 , wherein the first STI sidewall is coplanar with the first gate sidewall and wherein the second STI sidewall is coplanar with the second gate sidewall.

3. The semiconductor device of claim 1 , wherein the gate cut stressor is formed of a different material relative to the first STI and relative to the second STI.

4. The semiconductor device of claim 1 , wherein the second gate cut stressor material is directly upon a top surface of the first gate cut stressor material.

5. The semiconductor device of claim 1 , wherein the first gate cut stressor material is a liner and the second gate cut stressor material is directly upon the liner.

6. The semiconductor device of claim 1 , further comprising:
a first gate cap within the first device region, the first gate cap upon the first gate, the first gate cap comprising a first gate cap sidewall that faces the second device region;
a second gate cap within the second device region, the second gate cap upon the second gate, the second gate cap comprising a second gate cap sidewall that faces the first device region; and
wherein the gate cut stressor is further upon the first gate cap sidewall and upon the second gate cap sidewall.

7. A semiconductor device comprising:
a substrate comprising a planar top surface;
a first gate cut stressor within a first gate cut region that separates a first transistor region from a second transistor region, wherein the first gate cut stressor is directly upon the planar top surface and applies a first tensile force to a first gate perpendicular to a first channel in the first transistor region and to a second gate perpendicular to a second channel in the second transistor region; and
a second gate cut stressor within a second gate cut region that separates a third transistor region from a fourth transistor region, wherein the second gate cut stressor is directly upon the planar top surface and applies a second tensile force to a third gate perpendicular to a third channel in the third transistor region and to a fourth gate perpendicular to a fourth channel in the fourth transistor region, wherein the second gate cut stressor is formed of a different material relative to the first gate cut stressor.

8. The semiconductor device of claim 7 , wherein each of the first transistor region, the second transistor region, the third transistor region, and the fourth transistor region comprise:
a shallow trench isolation (STI) directly upon the planar top surface;
a gate directly upon the STI; and
a gate cap directly upon the gate.

9. The semiconductor device of claim 8 , wherein the first gate cut stressor physically connects the first transistor region STI with the second transistor region STI and wherein the first gate cut stressor further physically connects the first transistor region gate with the second transistor region gate.

10. The semiconductor device of claim 9 , wherein the second gate cut stressor physically connects the third transistor region STI with the fourth transistor region STI and wherein the second gate cut stressor further physically connects the third transistor region gate with the fourth transistor region gate.

11. The semiconductor device of claim 10 , wherein the first transistor region further comprises an N-type transistor, wherein the second transistor region further comprises a P-type transistor, wherein the third transistor region further comprises an N-type transistor, and wherein the fourth transistor region further comprises a P-type transistor.

12. The semiconductor device of claim 10 , wherein the first transistor region further comprises an first N-type transistor, wherein the second transistor region further comprises a second N-type transistor, wherein the third transistor region further comprises a first P-type transistor, and wherein the fourth transistor region further comprises a second P-type transistor.

13. The semiconductor device of claim 10 , wherein the first transistor region further comprises an first P-type transistor, wherein the second transistor region further comprises a second P-type transistor, wherein the third transistor region further comprises a first N-type transistor, and wherein the fourth transistor region further comprises a second N-type transistor.

14. The semiconductor device of claim 10 , wherein the first gate cut stressor physically connects the first transistor region gate cap with the second transistor region gate cap.

15. The semiconductor device of claim 14 , wherein the second gate cut stressor physically connects the third transistor region gate cap with the fourth transistor region gate cap.

16. A semiconductor device comprising:
a first gate associated with a first transistor;
a second gate associated with a second transistor;
a gate cut region adequately electrically separating a first sidewall of the first gate from a second sidewall of the second gate; and
a first gate cut stressor comprising a first gate cut stressor material and a second gate cut stressor material directly upon the first gate cut stressor material, the second gate cut stressor material different from the first gate cut stressor material, the first gate cut stressor directly connected to the first sidewall of the first gate and directly connected to the sidewall of the second gate, wherein the first gate cut stressor applies a first tensile force against the first gate substantially perpendicular to the first sidewall and applies the first tensile force against the second gate substantially perpendicular to the second sidewall.

17. The semiconductor device of cla

Assignees

• IBM

Inventors

• Zhou Huimei
• Greene Andrew M
• Belyansky Michael P
• Gluschenkov Oleg
• Robison Robert
• Li Juntao
• Conti Richard A
• Lie Fee Li

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title