Top via on subtractively etched conductive line

Patent metadata

Field	Value
Publication number	US-12598970-B2
Application number	US-202217683579-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	Mar 17, 2020
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

First claim

What is claimed is:

1 . A semiconductor device including a self-aligned top via, comprising:
a substrate; a first structure disposed on the substrate, the first structure including a self-aligned via disposed on a first conductive line, the first conductive line having a tapered geometry with a top width being more narrow than a bottom width resulting from a subtractive etch process, the self-aligned via having a top surface; and a second structure disposed on the substrate, the second structure including a plug disposed on a second conductive line, the second conductive line having a tapered geometry with a top width being more narrow than a bottom width resulting from the subtractive etch process, the plug having a top surface in a same plane as the top surface of the self-aligned via.

2 . The device of claim 1 , further comprising dielectric material disposed on the substrate separating the first structure from the second structure.

3 . The device of claim 2 , wherein the dielectric material separating the first structure from the second structure includes a conformal barrier layer disposed along sidewalls of the first structure and the second structure, and a dielectric layer disposed on the conformal barrier layer.

4 . The device of claim 1 , wherein the plug includes dielectric material.

5 . The device of claim 3 , wherein the first conductive line is recessed selective to the dielectric layer.

6 . The device of claim 1 , wherein the second conductive line is an exposed conductive line, the second conductive line being a recessed conductive line.

7 . The device of claim 1 , further comprising a second plug on the second conductive line, the second conductive line being a recessed conductive line.

8 . A semiconductor device including a self-aligned top via, comprising:
a substrate; a first structure disposed on the substrate, the first structure including a self-aligned via disposed on a first recessed conductive line, the first recessed conductive line having a tapered geometry with a top width being more narrow than a bottom width resulting from a subtractive etch process, the self-aligned via having a top surface; and a self-aligned top via opening formed on the first recessed conductive line; and a second structure disposed on the substrate, the second structure including a plug disposed on a second conductive line, the second recessed conductive line having a tapered geometry with a top width being more narrow than a bottom width resulting from the subtractive etch process, the plug having a top surface in a same plane as the top surface of the self-aligned via.

9 . The device of claim 8 , further comprising dielectric material disposed on the substrate separating the first structure from the second structure.

10 . The device of claim 9 , wherein the dielectric material separating the first structure from the second structure includes a conformal barrier layer disposed along sidewalls of the first structure and the second structure, and a dielectric layer disposed on the conformal barrier layer.

11 . The device of claim 8 , wherein the plug includes dielectric material.

12 . The device of claim 10 , wherein the first recessed conductive line is recessed selective to the dielectric layer.

13 . The device of claim 8 , wherein the second conductive line is an exposed conductive line, the second conductive line being a recessed conductive line.

Assignees

• Int Business Machines Corporation

Inventors

• Anderson Brent
• Clevenger Lawrence A
• Choi Kisik
• Lanzillo Nicholas Anthony
• Penny Christopher J
• Robison Robert

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/6548

  by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title