Top via with damascene line and via

Patent metadata

Field	Value
Publication number	US-11894265-B2
Application number	US-202117479346-A
Country	US
Kind code	B2
Filing date	Sep 20, 2021
Priority date	Jan 15, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

First claim

What is claimed is:

1. A top via, comprising:
a trench plate on a conductive line wherein a gap is formed between an etch stop layer and the trench plate;
a conductive trench plug on the trench plate;
channel plate on the conducive trench plug;
a conductive channel plug on the channel plate; and
a barrier layer on the conductive channel plug, channel plate, conductive trench plug, and trench plate.

2. The top via of claim 1 , further comprising a second trench plate and a second conductive trench plug on a second conductive line, wherein the barrier layer is also on the second trench plate, second conductive trench plug, and the second conductive line.

3. The top via of claim 2 , further comprising a capping layer on the harrier layer.

4. The top via of claim 3 , wherein the etch stop layer is in contact with the barrier layer.

5. The top via of claim 4 , further comprising a second etch stop layer on the capping layer.

6. The top via of claim 1 , wherein the barrier layer is in direct contact with the trench plate and the conductive line.

7. The top via of claim 6 , wherein the trench plate is a conductive metal selected from the group consisting of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), cobalt (Co), and combinations thereof.

8. The top via of claim 7 , wherein the barrier layer is directly on an etch stop layer, conductive trench plug, and conductive channel plug.

9. The top via of claim 8 , wherein the barrier layer is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and combinations thereof.

10. A top via, comprising:
air etch stop layer on a fill layer;
a conductive line in the fill layer;
a trench plate on a conductive line;
a gap between the etch stop layer and the trench plate;
a conductive trench plug on the trench plate;
a channel plate on the conductive trench plug;
conductive channel plug on the channel plate; and
a barrier layer on the conductive channel plug, channel plate, conductive trench plug, and trench plate.

11. The top via of claim 10 , wherein the barrier layer is in the gap between the etch stop layer and the trench plate.

12. The top via of claim 11 , further comprising a capping layer on the barrier layer.

13. The top via of claim 12 , farther comprising a second etch stop layer on the capping layer, conductive channel plug, and the barrier layer.

14. The top via of claim 13 , wherein the harrier layer is directly on the conductive channel plug and conductive trench plug.

15. A top via comprising:
a first etch stop layer on a fill layer;
a conductive line in the fill layer;
a trench plate on a conductive line, wherein there is a gap between the first etch stop layer and the trench plate;
a conductive trench plug on the trench plate;
a channel plate on the conductive trench plug;
a conductive channel plug on the channel plate; and
a harrier layer directly on the first etch stop layer, conductive line, conductive channel plug, channel plate, conductive trench Ow, and trench plate.

16. The top via of claim 15 , further comprising a second etch stop layer directly on the barrier layer and the conductive channel plug.

17. The top via of claim 16 , further comprising an interlayer dielectric layer on the second etch stop layer.

18. The top via of claim 16 , further comprising a second trench plate and, a second conductive bench plug on a second conductive line, wherein the barrier layer is also on the second trench plate, second conductive trench plug, and the second conductive line.

19. The top via of claim 16 , wherein the barrier layer is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and combinations thereof.

Assignees

• IBM

Inventors

• Clevenger Lawrence A
• Anderson Brent
• Choi Kisik
• Lanzillo Nicholas Anthony
• Penny Christopher J
• Robison Robert

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title