Stepped top via for via resistance reduction

Patent metadata

Field	Value
Publication number	US-11670542-B2
Application number	US-202217570445-A
Country	US
Kind code	B2
Filing date	Jan 7, 2022
Priority date	Feb 11, 2020
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

First claim

What is claimed is:

1. An integrated circuit comprising:
a conductive line in a dielectric layer;
a stepped top via on a surface of the conductive line, the stepped top via comprising a top portion having a first width and a bottom portion having a second width greater than the first width; and
an etch stop layer on the dielectric layer, the etch stop layer in direct contact with a top surface of the bottom portion of the stepped top via and a sidewall of the top portion of the stepped top via.

2. The integrated circuit of claim 1 , wherein sidewalls of the top portion are aligned to an opening in the etch stop layer.

3. The integrated circuit of claim 2 , wherein the top portion is centered over the bottom portion.

4. The integrated circuit of claim 3 , wherein the conductive line is recessed from a top surface of the dielectric layer.

5. The integrated circuit of claim 4 further comprising a second dielectric layer on the recessed surface of the conductive line, the second dielectric layer comprising a material selected such that the second dielectric layer can be removed selective to the dielectric layer.

6. The integrated circuit of claim 5 , wherein a sidewall of the second dielectric layer is in direct contact with sidewalls of the bottom portion of the stepped top via.

7. The integrated circuit of claim 6 , wherein a portion of the etch stop layer is in direct contact with a top surface of the second dielectric layer.

Assignees

• IBM

Inventors

• Anderson Brent Alan
• Clevenger Lawrence A
• Penny Christopher J
• Choi Kisik
• Lanzillo Nicholas Anthony
• Robison Robert

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title