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Patent metadata

Field	Value
Publication number	US-11600565-B2
Application number	US-202117496252-A
Country	US
Kind code	B2
Filing date	Oct 7, 2021
Priority date	Jan 10, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first metallization layer disposed on a first etch stop layer, wherein the first metallization layer comprises a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer, wherein a height of the first conductive line is greater than a height of the second conductive line;
a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer;
a first conductive material disposed on a top surface of the first conductive line in the first via; and
a second conductive material disposed on a top surface of the second conductive line in the second via.

2. The semiconductor structure of claim 1 , further comprising:
a second etch stop layer disposed on a portion of a top surface of the second dielectric layer and the first conductive material; and
a third dielectric layer disposed on the second etch stop layer.

3. The semiconductor structure of claim 2 , further comprising:
a second metallization layer disposed on the first via layer, wherein the second metallization layer comprises a first conductive line disposed on the top surface of the second dielectric layer and the first conductive material and in contact with sidewalls of the third dielectric layer and the second etch stop layer; and a second conductive line disposed on the top surface of the second dielectric layer and the second conductive material and in contact with sidewalls of the third dielectric layer and the second etch stop layer.

4. The semiconductor structure of claim 3 , further comprising:
a second via layer comprising a fourth dielectric layer disposed on a top surface of the second metallization layer and a first via and a second via in the fourth dielectric layer; and
a third conductive material disposed in the first via and the second via in the second via layer.

5. The semiconductor structure of claim 3 , wherein a width of the first conductive line of the second metallization layer is greater than a width of the second conductive line of the second metallization layer.

6. The semiconductor structure of claim 4 , wherein the first via and the second via of the second via layer have the same height.

7. The semiconductor structure of claim 1 , wherein the first etch stop layer is disposed on a semiconductor substrate.

8. The semiconductor structure of claim 1 , wherein the first dielectric layer comprises a low-k dielectric material.

9. The semiconductor structure of claim 4 , wherein the first conductive material, the second conductive material and the third conductive material are independently selected from the group consisting of aluminum, chromium, hafnium, iridium, molybdenum, niobium, osmium, rhenium, rhodium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and alloys thereof.

10. The semiconductor structure of claim 1 , wherein a top surface of the first conductive material and a top surface of the second conductive material are coplanar.

11. An integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a first metallization layer disposed on a first etch stop layer, wherein the first metallization layer comprises a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer, wherein a height of the first conductive line is greater than a height of the second conductive line;
a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer;
a first conductive material disposed on a top surface of the first conductive line in the first via; and
a second conductive material disposed on a top surface of the second conductive line in the second via.

12. The integrated circuit of claim 11 , further comprising:
a second etch stop layer disposed on a portion of a top surface of the second dielectric layer and the first conductive material; and
a third dielectric layer disposed on the second etch stop layer.

13. The integrated circuit of claim 12 , further comprising:
a second metallization layer disposed on the first via layer, wherein the second metallization layer comprises a first conductive line disposed on the top surface of the second dielectric layer and the first conductive material and in contact with sidewalls of the third dielectric layer and the second etch stop layer; and a second conductive line disposed on the top surface of the second dielectric layer and the second conductive material and in contact with sidewalls of the third dielectric layer and the second etch stop layer.

14. The integrated circuit of claim 13 , further comprising:
a second via layer comprising a fourth dielectric layer disposed on a top surface of the second metallization layer and a first via and a second via in the fourth dielectric layer; and
a third conductive material disposed in the first via and the second via in the second via layer.

15. The integrated circuit of claim 13 , wherein a width of the first conductive line of the second metallization layer is greater than a width of the second conductive line of the second metallization layer.

16. The integrated circuit of claim 14 , wherein the first via and the second via of the second via layer have the same height.

17. The integrated circuit of claim 11 , wherein a top surface of the first conductive material and a top surface of the second conductive material are coplanar.

18. A method, comprising:
forming a first metallization layer on a first etch stop layer comprising a first conductive line and a second conductive line in a first dielectric layer;
selectively recessing a portion of the second conductive line, wherein a height of the first conductive line is greater than a height of the second conductive line;
depositing a second dielectric layer in the recessed portion of the second conductive line and on a top surface of the first conductive line;
forming a first via layer comprising a first via in the second dielectric layer and exposing a top surface of the second conductive line; and
depositing a first conductive material in the first via.

19. The method of claim 18 , further comprising:
depositing a second etch stop layer on a top surface of the second dielectric layer and the first conductive material; and
depositing a third dielectric layer on the second etch stop layer.

20. The method of claim 19 , further comprising:
removing a portion of the third dielectric layer and the second etch stop layer and exposing the top surface of the second dielectric layer and the first conductive material.

Assignees

• IBM

Inventors

• Anderson Brent Alan
• Clevenger Lawrence A
• Penny Christopher J
• Choi Kisik
• Lanzillo Nicholas Anthony
• Robison Robert

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4405

  the principal metal being aluminium · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title