Fully aligned top vias

Patent metadata

Field	Value
Publication number	US-11854884-B2
Application number	US-202117551531-A
Country	US
Kind code	B2
Filing date	Dec 15, 2021
Priority date	Nov 8, 2019
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

First claim

What is claimed is:

1. An aligned top via, comprising:
a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias;
a spacer layer aligned to an upper surface of the fill layer;
an etch-stop layer on at least a portion of the spacer layer and at least a portion of one of the one or more vias;
one or more cover layer regions on the etch-stop layer; and
a plurality of openings, wherein each of the openings is adjacent to at least one of the one or more cover layer regions, and one of the plurality of openings is at least partially aligned with one of the one or more vias, and another of the plurality of openings is not aligned with the one or more vias.

2. The aligned top via of claim 1 , further comprising a conductive fill in each of the plurality of openings, wherein the conductive fill is in electrical contact with one of the one or more vias aligned with one of the plurality of openings.

3. The aligned top via of claim 2 , wherein the spacer layer has a thickness in a range of about 1 nm to about 15 nm.

4. The aligned top via of claim 3 , wherein the spacer layer has a thickness in a range of about 5 nm to about 10 nm.

5. The aligned top via of claim 4 , wherein the spacer layer is an electrically insulating dielectric material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon boronitride (SiBN), silicon carbonitride (SiCN), silicon boro carbonitride (SiBCN), low-k dielectric materials, and combinations thereof.

6. The aligned top via of claim 5 , wherein the etch-stop layer is a metal compound selected from the group consisting of aluminum nitride (AlN), titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), titanium-aluminum nitride (TiAlN), titanium carbide (TiC), tamtalum carbide (TaC), titanium-aluminum carbide (TiAlC), aluminum oxide (AlO), and combinations thereof.

7. The aligned top via of claim 6 , wherein an increased distance between one conductive fill and the closest point of an adjacent via of the one or more vias is in a range of about 5 nm to about 20 nm.

8. The aligned top via of claim 7 , wherein the spacer layer is a different electrically insulating dielectric material from the fill layer.

9. An aligned top via, comprising:
a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias;
a spacer layer aligned to an upper surface of the fill layer;
an etch-stop layer on at least a portion of the spacer layer and at least a portion of one of the one or more vias, wherein portions of the etch-stop layer are at different elevations;

one or more cover layer regions on the etch-stop layer; and
a plurality of openings, wherein each of the openings is adjacent to at least one of the one or more cover layer regions, and one of the plurality of openings is at least partially aligned with one of the one or more vias, and another of the plurality of openings is not aligned with the one or more vias.

10. The aligned top via of claim 9 , wherein the fill layer is an electrically insulating dielectric material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon boronitride (SiBN), silicon carbonitride (SiCN), silicon boro carbonitride (SiBCN), low-k dielectric materials, and combinations thereof.

11. The aligned top via of claim 10 , wherein the spacer layer is carbon doped silicon oxide or organosilicate glasses (SiO:C).

12. The aligned top via of claim 11 , wherein the etch-stop layer is a metal compound selected from the group consisting of aluminum nitride (AlN), titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), titanium-aluminum nitride (TiAlN), titanium carbide (TiC), tamtalum carbide (TaC), titanium-aluminum carbide (TiAlC), aluminum oxide (AlO), and combinations thereof.

13. The aligned top via of claim 12 , wherein the spacer layer has a thickness in a range of about 1 nm to about 15 nm.

14. The aligned top via of claim 13 , further comprising a conductive fill in each of the plurality of openings, wherein the conductive fill is in electrical contact with one of the one or more vias aligned with one of the plurality of openings.

15. An aligned top via, comprising:
a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias;
a spacer layer aligned to an upper surface of the fill layer, wherein the spacer layer has a thickness in a range of about 1 nm to about 15 nm;
an etch-stop layer on at least a portion of the spacer layer and at least a portion of one of the one or more vias;
one or more cover layer regions on the etch-stop layer;
a plurality of openings, wherein each of the openings is adjacent to at least one of the one or more cover layer regions, and one of the plurality of openings is at least partially aligned with one of the one or more vias, and another of the plurality of openings is not aligned with the one or more vias; and
a conductive fill in each of the plurality of openings, wherein the conductive fill is in electrical contact with one of the one or more vias aligned with one of the plurality of openings.

16. The aligned top via of claim 15 , wherein an increased distance between one conductive fill and the closest point of an adjacent via of the one or more vias is in a range of about 5 nm to about 20 nm compared to one conductive fill and the closest point of an adjacent via without a spacer layer.

17. The aligned top via of claim 16 , wherein the spacer layer is a different electrically insulating dielectric material from the fill layer.

18. The aligned top via of claim 17 , wherein portions of the etch-stop layer are at different elevations.

19. The aligned top via of claim 18 , wherein the cover layer regions are porous organosilicate glass (pSiCOH) or aluminum oxide (AlO).

20. The fully aligned top via of claim 19 , wherein the spacer layer is an electrically insulating dielectric material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon boronitride (SiBN), silicon carbonitride (SiCN), silicon boro carbonitride (SiBCN), low-k dielectric materials, and combinations thereof.

Assignees

• IBM

Inventors

• Lanzillo Nicholas Anthony
• Motoyama Koichi
• Ghosh Somnath
• Penny Christopher J
• Robison Robert
• Clevenger Lawrence A

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title