Source and drain contact cut last process to enable wrap-around-contact

Patent metadata

Field	Value
Publication number	US-11757012-B2
Application number	US-201916687736-A
Country	US
Kind code	B2
Filing date	Nov 19, 2019
Priority date	Nov 13, 2018
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a source or drain (S/D) contact liner on S/D regions, wherein an upper portion of the S/D regions comprises the S/D contact liner while a lower portion of the S/D regions is free of the S/D contact liner, wherein the upper portion is formed with a first slope having a first rise extending upward away from a shallow trench isolation (STI) region toward at least one fin, wherein the lower portion is formed with a second slope having a second rise extending upward away from both the at least one fin and the STI region, the first rise of the upper portion and the second rise of the lower portion extending upward in different directions;
a silicide layer formed around the upper portion and the lower portion of the S/D regions, the lower portion being underneath the upper portion, wherein the silicide layer is formed between the S/D contact liner and the S/D regions, the silicide layer formed on the lower portion being in direct contact with a fill material such that there is no intervening layer between the silicide layer on the lower portion and the fill material, wherein a portion of the S/D contact liner on the upper portion is formed with the first slope having the first rise while the silicide layer on the lower portion is formed with the second slope having the second rise, the fill material being an insulating material formed directly on the STI region, wherein a part of the fill material is sandwiched in between and in direct contact with both a portion of the silicide layer on the lower portion and the STI region, the S/D regions formed of epitaxial material, wherein the fin extends through the lower portion into the upper portion of the epitaxial material such that the fin extends above any of the silicide layer formed around the lower portion of the S/D regions; and
S/D contacts formed on the S/D contact liner over the S/D regions.

2. The semiconductor device of claim 1 , wherein the S/D regions are formed over one or more fins, the S/D regions being formed with a diamond shape, wherein a part of the diamond shape comprises the upper portion formed with the first slope while another part of the diamond shape comprises the lower portion formed with the second slope, the fin extending above vertices of the diamond shape connecting the upper portion to the lower portion.

3. The semiconductor device of claim 1 , wherein the S/D contact liner includes a first material formed directly on the S/D regions and a second material formed on the first material.

4. The semiconductor device of claim 3 , wherein the silicide layer around the S/D regions is formed of the first material and of epitaxial material of the S/D regions, after annealing.

5. The semiconductor device of claim 1 , wherein the fill material is formed on the S/D regions.

6. The semiconductor device of claim 1 , wherein the fill material is formed adjacent to the S/D contact liner.

7. The semiconductor device of claim 1 , wherein the fill material is formed on the silicide layer.

8. The semiconductor device of claim 7 , wherein the fill material is a dielectric material.

9. The semiconductor device of claim 7 , wherein the fill material comprises a strained dielectric material.

10. The semiconductor device of claim 7 , wherein the fill material comprises nitride.

11. The semiconductor device of claim 7 , wherein the fill material comprises oxide.

12. The semiconductor device of claim 1 , wherein the silicide layer is a wrap-around-contact (WAC).

13. The semiconductor device of claim 1 , wherein the silicide layer wraps around the S/D regions.

14. The semiconductor device of claim 1 , wherein the silicide layer comprises titanium.

15. The semiconductor device of claim 1 , wherein the S/D regions comprise p-type dopants.

16. The semiconductor device of claim 1 , wherein the S/D regions comprise n-type dopants.

17. The semiconductor device of claim 1 , wherein the S/D contacts comprise metal.

18. The semiconductor device of claim 1 , wherein the S/D contacts comprise tungsten.

19. The semiconductor device of claim 1 , wherein the S/D contacts comprise cobalt.

20. The semiconductor device of claim 1 , wherein the S/D contact liner comprises a stack of titanium and titanium nitride.

Assignees

• IBM

Inventors

• Greene Andrew
• Guo Dechao
• Yamashita Tenko
• Basker Veeraraghavan S
• Robison Robert
• Rahman Ardasheir

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D84/834

  comprising FinFETs · CPC title