Self-aligned C-shaped vertical field effect transistor

Patent metadata

Field	Value
Publication number	US-12268030-B2
Application number	US-202117446784-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Sep 2, 2021
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

A self-aligned C-shaped vertical field effect transistor includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate. The fin structure has two adjacent vertical segments with rounded ends that extend perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment that extends between and connects the two adjacent vertical segments. An opening is located between the two adjacent vertical segments on a side of the fin structure opposite to the horizontal segment.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate having an uppermost surface; and
a fin structure on the uppermost surface of the semiconductor substrate, the fin structure including two adjacent vertical segments with rounded ends extending perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment extending between and connecting the two adjacent vertical segments, wherein an opening is located between the two adjacent vertical segments on a side of the fin structure opposing the horizontal segment.

2. The semiconductor structure of claim 1 , wherein the two adjacent vertical segments connected by the horizontal segment and having the opening on the side of the fin structure opposing the horizontal segment defines a C-shaped fin architecture in the semiconductor structure.

3. The semiconductor structure of claim 1 , further comprising:
a first region having a first polarity, the first region comprising a first row of fin structures; and
a second region adjacent to the first region, the second region having a second polarity and comprising a second row of fin structures, wherein the first polarity and the second polarity are equal.

4. The semiconductor structure of claim 3 , wherein the horizontal segment of each fin structure in the first row of fin structures faces the horizontal segment of each fin structure in the second row of fin structures.

5. The semiconductor structure of claim 3 , further comprising:
a third region adjacent to the second region, the third region having a third polarity and comprising a third row of fin structures, wherein the third polarity is different from the first polarity and the second polarity.

6. The semiconductor structure of claim 5 , wherein the opening of each fin structure in the second row of fin structures faces the opening of each fin structure in the second row of fin structures.

7. The semiconductor structure of claim 5 , wherein neighboring fin structures in the first row of fin structures, neighboring fin structures in the second row of fin structures, and neighboring fin structures in the third row of fin structures are each separated by a first distance a, and wherein the first row of fin structures, the second row of fin structures, and the third row of fin structures are each separated by a second distance b, the first distance a being smaller than the second distance b.

8. A semiconductor structure comprising:
a semiconductor substrate;
a first region and a second region on the semiconductor substrate, the first region being adjacent to the second region and separated from the second region by a first space, the first region and the second region having a first polarity;
a third region on the semiconductor substrate adjacent to the second region and separated from the second region by a second space, the third region having a second polarity that is different from the first polarity; and
a row of fin structures disposed on each of the first region, the second region and the third region, each fin structure in the row of fin structures including two adjacent vertical segments with rounded ends extending perpendicularly from an uppermost surface of the semiconductor substrate and a horizontal segment extending between and connecting the two adjacent vertical segments, wherein an opening is located between the two adjacent vertical segments on a side of the fin structure opposing the horizontal segment.

9. The semiconductor structure of claim 8 , wherein the horizontal segment of each fin structure in the row of fin structures disposed on the first region faces the horizontal segment of each fin structure in the row of fin structures disposed on the second region.

10. The semiconductor structure of claim 8 , wherein the opening of each fin structure in the row of fin structures disposed on the second region faces the opening of each fin structure in the row of fin structures disposed on the third region.

11. The semiconductor structure of claim 8 , wherein a fin structure in the row of fin structures is separated from another fin structure in the same row of fin structures by a first distance a, wherein the first distance a is smaller than a second distance b separating each row of fin structures.

12. A method of forming a semiconductor structure, comprising:
forming a plurality of fin structures on an uppermost surface of a semiconductor substrate, each fin structure in the plurality of fin structures comprising:
two adjacent vertical segments with rounded ends extending perpendicularly from the uppermost surface of the semiconductor substrate, and
a horizontal segment extending between and connecting the two adjacent vertical segments, wherein an opening is located between the two adjacent vertical segments on a side of each fin structure opposing the horizontal segment.

13. The method of claim 12 , wherein forming the plurality of fin structures further comprises:
forming a hardmask layer on the semiconductor substrate;
transferring a fin pattern to the hardmask layer defining the plurality of fin structures; and
forming the plurality of fin structures on the uppermost surface of the semiconductor substrate according to the transferred fin pattern.

14. The method of claim 12 , wherein the two adjacent vertical segments connected by the horizontal segment and having the opening on the side of each fin structure opposing the horizontal segment defines a C-shaped fin architecture in the semiconductor structure.

15. The method of claim 13 , wherein transferring the fin pattern further comprising:
forming an array of mandrels on the hardmask layer;
forming sidewall image transfer spacers surrounding the array of mandrels;
forming a oxide layer above the hardmask layer, the array of mandrels and the sidewall image transfer spacers; and
etching the oxide layer to expose top and lateral portions of the sidewall image transfer spacers.

16. The method of claim 15 , further comprising:
depositing an organic planarization layer; and
patterning the organic planarization layer to cover a space between regions of the semiconductor substrate having the same polarity and exposing a space between regions of the semiconductor substrate having opposing polarities.

17. The method of claim 16 , further comprising:
removing portions of the sidewall image transfer spacers not covered by the organic planarization layer using an isotropic etch process; and
removing the organic planarization layer.

18. The method of claim 17 , further comprising:
removing the array of mandrels selective to the sidewall image transfer spacers.

19. The method of claim 12 , wherein the horizontal segment of a fin structure disposed on a first region faces the horizontal segment of a fin structure disposed on a second region when the first region and the second region have the same polarity.

20. The method of claim 19 , wherein the opening of a fin structure disposed on the first region faces the opening of a fin structure disposed on the second region when the first region and the second region have different polarities.

Assignees

• IBM

Inventors

• Xie Ruilong
• Robison Robert
• Jagannathan Hemanth
• Strane Jay William

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title