Looped long channel field-effect transistor

Patent metadata

Field	Value
Publication number	US-12356685-B2
Application number	US-202117486911-A
Country	US
Kind code	B2
Filing date	Sep 28, 2021
Priority date	Sep 28, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first source/drain region;
a second source/drain region;
an isolation region between and electrically isolating the first source/drain region and the second source/drain region, wherein the first source/drain region and the second source/drain region directly contact opposing vertical side walls of the isolation region;
a channel having a first end adjoining the first source/drain region and a second end adjoining the second source/drain region such that the first source/drain region and the second source/drain region separate the opposing vertical side walls of the isolation region from sides of the channel, wherein the first source/drain region, the second source/drain region, the isolation region and the channel form a closed loop; and
a gate stack adjoining the channel.

2. The semiconductor structure of claim 1 , further including a semiconductor substrate and a semiconductor fin extending vertically from the semiconductor substrate, the channel being comprised of the semiconductor fin, the first end of the channel comprising a first end portion of the semiconductor fin, the second end of the channel comprising a second end portion of the semiconductor fin.

3. The semiconductor structure of claim 2 , further including a first dielectric spacer adjoining a first pair of sidewalls of the semiconductor fin and positioned between the gate stack and the first source/drain region and a second dielectric spacer adjoining a second pair of sidewalls of the semiconductor fin and positioned between the gate stack and the second source/drain region, the first dielectric spacer electrically isolating the gate stack and the first source/drain region, the second dielectric spacer electrically isolating the gate stack and the second source/drain region.

4. The semiconductor structure of claim 3 , wherein the first source/drain region, the second source/drain region, the channel and the gate stack comprise a long channel lateral transport transistor.

5. The semiconductor structure of claim 4 , further including a vertical transport transistor on the substrate, the vertical transport transistor including a channel comprising a vertical fin extending from the semiconductor substrate, a gate structure adjoining the channel, a bottom source/drain region, and a top source/drain region.

6. The semiconductor structure of claim 5 , further including a top spacer adjoining the gate structure and electrically isolating the gate structure from the top source/drain region of the vertical transport transistor, the top spacer further adjoining the gate stack of the long channel lateral transport transistor.

7. The semiconductor structure of claim 6 , further including a bottom spacer electrically isolating the gate structure and the bottom source/drain region of the vertical transport transistor, the bottom spacer further adjoining the gate stack of the long channel lateral transport transistor.

8. The semiconductor structure of claim 1 , wherein the channel is comprised of a semiconductor fin extending from a semiconductor substrate, the first source/drain region being epitaxial with respect to a first end portion of the semiconductor fin, the second source/drain region being epitaxial with respect to a second end portion of the semiconductor fin.

9. The semiconductor structure of claim 8 , further including a first interlevel dielectric layer over the semiconductor substrate, the isolation region comprising a portion of the interlevel dielectric layer.

10. The semiconductor structure of claim 9 , further including:
a top dielectric spacer above the first interlevel dielectric layer, the semiconductor fin, and the gate stack;
a second interlevel dielectric layer over the top dielectric spacer;
a first source/drain contact extending through the second interlevel dielectric layer and the top dielectric spacer, the first source/drain contact having a bottom end in direct contact with the first source/drain region; and
a second source/drain contact extending through the second interlevel dielectric layer and the top dielectric spacer, the second source/drain contact having a bottom end in direct contact with the second source/drain region.

11. The semiconductor structure of claim 10 , wherein:
the first source/drain region, the second source/drain region, the channel and the gate stack comprise a long channel lateral transport transistor, and wherein the top dielectric spacer adjoins the vertical side walls of the isolation region.

12. The semiconductor structure of claim 11 , further including a first dielectric spacer adjoining a first pair of sidewalls of the semiconductor fin and positioned between the gate stack and the first source/drain region and a second dielectric spacer adjoining a second pair of sidewalls of the semiconductor fin and positioned between the gate stack and the second source/drain region, the first dielectric spacer electrically isolating the gate stack and the first source/drain region, the second dielectric spacer electrically isolating the gate stack and the second source/drain region.

13. The semiconductor structure of claim 12 , further including a top spacer having a first portion between the first source/drain region and the isolation region and a second portion between the second source/drain region and the isolation region.

14. The semiconductor structure of claim 1 , wherein the channel contacts sides of the first source/drain region and the second source/drain region directly opposite from the opposing vertical side walls of the isolation region.

15. The semiconductor structure of claim 1 , wherein the gate stack contacts other sides of the channel directly opposite from the first source/drain region and the second source/drain region.

16. An array of long channel field-effect transistors, comprising:
a semiconductor fin including a plurality fin segments, the plurality of fin segments being separated by openings in the semiconductor fin;
each of a plurality of the openings in the semiconductor fin containing:
a first epitaxial source/drain region epitaxial with respect to an end portion of one segment of the plurality of fin segments;
a second epitaxial source/drain region epitaxial with respect to an end portion of another segment of the plurality of fin segments;
an isolation region between and electrically isolating the first epitaxial source/drain region and the second epitaxial source/drain region, wherein the first epitaxial source/drain region and the second epitaxial source/drain region directly contact opposing vertical side walls of the isolation region such that the first epitaxial source/drain region and the second epitaxial source/drain region separate the opposing vertical side walls of the isolation region from the one segment of the plurality of fin segments and from the other segment of the plurality of fin segments;

the plurality of fin segments comprising a plurality of channel regions; and
a plurality of gate stacks adjoining, respectively, each of the plurality of channel regions;
the first epitaxial source/drain regions, the second epitaxial source/drain regions, the isolation regions and the plurality of fin segments forming a closed loop.

17. The array of long channel field-effect transistors of claim 16 , further including a plurality of dielectric spacers electrically isolating, respectively, each of the first epitaxial source/drain regions and the second epitaxial source/drain regions from the plurality gate stacks, each of the dielectric spacers adjoining a sidewall of

Assignees

• IBM

Inventors

• Xie Ruilong
• Rahman Ardasheir
• Jagannathan Hemanth
• Robison Robert
• Anderson Brent
• Wu Heng

Classifications

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title