CMOS architecture with thermally stable silicide gate workfunction metal
US-12575184-B2 · Mar 10, 2026 · US
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Phan Anh patents
Phan Anh is listed as an inventor on 102 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Phan Anh |
| Total patents | 102 |
| First publication | Dec 14, 2017 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Transistor assemblies with patterned back side-filled isolation regions
US-2025301779-A1 · Sep 25, 2025 · US
Recessed oxide and seam-first etch for air-gapped isolation walls
US-2025210412-A1 · Jun 26, 2025 · US
Air-gapped isolation walls
US-2025210522-A1 · Jun 26, 2025 · US
Air gap insulation in place of gate spacers
US-2025098242-A1 · Mar 20, 2025 · US
Air gap insulation in place of gate spacers
US-2025098239-A1 · Mar 20, 2025 · US
Sideways vias in isolation areas to contact interior layers in stacked devices
US-12255137-B2 · Mar 18, 2025 · US
Forming an oxide volume within a fin
US-12224202-B2 · Feb 11, 2025 · US
Stacked source-drain-gate connection and process for forming such
US-12148806-B2 · Nov 19, 2024 · US
Backside contacts for semiconductor devices
US-2024371700-A1 · Nov 7, 2024 · US
Recent patents
Latest publications not already listed above.
Interconnect techniques for electrically connecting source/drain regions of stacked transistors
US-12107085-B2 · Oct 1, 2024 · US
Backside contacts for semiconductor devices
US-12080605-B2 · Sep 3, 2024 · US
Stacked forksheet transistors
US-2024234422-A1 · Jul 11, 2024 · US
Isolation wall stressor structures to improve channel stress and their methods of fabrication
US-12033896-B2 · Jul 9, 2024 · US
Epitaxial layer with substantially parallel sides
US-12020929-B2 · Jun 25, 2024 · US
Integrated circuit structures with cavity spacers
US-2024186398-A1 · Jun 6, 2024 · US
Stacked forksheet transistors
US-11996411-B2 · May 28, 2024 · US
Leave-behind protective layer having secondary purpose
US-11996408-B2 · May 28, 2024 · US
Sideways vias in isolation areas to contact interior layers in stacked devices
US-2024162141-A1 · May 16, 2024 · US
Stacked source-drain-gate connection and process for forming such
US-2024145557-A1 · May 2, 2024 · US
Sideways vias in isolation areas to contact interior layers in stacked devices
US-11942416-B2 · Mar 26, 2024 · US
Stacked source-drain-gate connection and process for forming such
US-11916118-B2 · Feb 27, 2024 · US
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach
US-2024047559-A1 · Feb 8, 2024 · US
Stacked trigate transistors with dielectric isolation and process for forming such
US-11894372-B2 · Feb 6, 2024 · US
Metallization structures for stacked device connectivity and their methods of fabrication
US-11869894-B2 · Jan 9, 2024 · US
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach
US-11830933-B2 · Nov 28, 2023 · US
Forming an oxide volume within a fin
US-2023377947-A1 · Nov 23, 2023 · US
Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches
US-2023369399-A1 · Nov 16, 2023 · US
Interconnect techniques for electrically connecting source/drain regions of stacked transistors
US-2023352481-A1 · Nov 2, 2023 · US
Sidewall interconnect metallization structures for integrated circuit devices
US-11776898-B2 · Oct 3, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 100 |
| Apple Inc | 2 |
| Lilak Aaron D | 2 |
| Huang Cheng Ying | 2 |
| Dewey Gilbert | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 98 |
| H10D88/00 | 78 |
| H10D88/01 | 70 |
| H10D30/6757 | 49 |
| H10D84/834 | 43 |