Sideways vias in isolation areas to contact interior layers in stacked devices

Patent metadata

Field	Value
Publication number	US-11942416-B2
Application number	US-201916457669-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 28, 2019
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first channel, wherein the first channel comprises a semiconductor;
a second channel positioned directly above the first channel, wherein the second channel comprises a semiconductor;
a source/drain (S/D) region, wherein the S/D region electrically couples the first channel to the second channel;
a first isolation region, wherein the first isolation region is parallel to a length direction of the first channel and the second channel, and wherein the first isolation region has a bottommost surface;
a second isolation region, wherein the second isolation region is substantially parallel to the first isolation region, wherein the first channel and the second channel are between the first isolation region and the second isolation region, and wherein the second isolation region has a bottommost surface at a same level as the bottommost surface of the first isolation region; and
a contact, wherein the contact is directly on a top surface of the S/D region and directly on a first outer sidewall surface of the S/D region, wherein the contact is directly on a top surface of the first isolation region.

2. The semiconductor device of claim 1 , wherein the first outer sidewall surface of the S/D region is substantially parallel to the length direction of the first channel.

3. The semiconductor device of claim 2 , wherein the contact is within the first isolation region.

4. The semiconductor device of claim 1 , wherein the first outer sidewall surface of the S/D region is substantially orthogonal to the length direction of the first channel.

5. The semiconductor device of claim 4 , wherein the contact is within a depopulated gate region.

6. The semiconductor device of claim 1 , wherein the contact extends over a second outer sidewall surface of the S/D region.

7. The semiconductor device of claim 1 , wherein the contact extends over a bottom surface of the S/D region.

8. The semiconductor device of claim 1 , further comprising:
a second contact, wherein the second contact is over a bottom surface of the S/D region.

9. The semiconductor device of claim 8 , wherein the second contact is over a second outer sidewall surface of the S/D region that is opposite from the first outer sidewall surface of the S/D region.

10. The semiconductor device of claim 1 , wherein the first channel and the second channel are a nanowire or a nanoribbon.

11. The semiconductor device of claim 1 , wherein the first channel is a fin, a nanowire, or a nanoribbon, and wherein the second channel is a different one of the fin, the nanowire, or the nanoribbon.

12. The semiconductor device of claim 1 , wherein the first channel and the second channel are included in a stack of a plurality of channels.

13. The semiconductor device of claim 1 , wherein the first isolation region comprises:
a first wall;
a second wall; and
a fill layer between the first wall and the second wall.

14. The semiconductor device of claim 13 , wherein a height of the first wall is less than a height of the second wall.

15. A semiconductor device, comprising:
a first channel, wherein the first channel comprises a semiconductor;
a second channel positioned directly above the first channel, wherein the second channel comprises a semiconductor;
a source/drain (S/D) region, wherein the S/D region electrically couples the first channel to the second channel;
a first isolation region, wherein the first isolation region is parallel to a length direction of the first channel and the second channel, and wherein the first isolation region comprises a first wall, a second wall, and a fill layer between the first wall and the second wall;
a second isolation region, wherein the second isolation region is substantially parallel to the first isolation region, and wherein the first channel and the second channel are between the first isolation region and the second isolation region; and
a contact, wherein the contact is directly on a top surface of the S/D region and directly on a first outer sidewall surface of the S/D region, wherein the contact is directly on a top surface of the first isolation region.

16. The semiconductor device of claim 15 , wherein a height of the first wall is less than a height of the second wall.

Assignees

• Intel Corp

Inventors

• Mannebach Ehren
• Lilak Aaron
• Yoo Hui Jae
• Morrow Patrick
• Phan Anh
• Rachmady Willy
• Huang Cheng-Ying
• Dewey Gilbert
• Mehandru Rishabh

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title