Leave-behind protective layer having secondary purpose

Patent metadata

Field	Value
Publication number	US-11996408-B2
Application number	US-202217726412-A
Country	US
Kind code	B2
Filing date	Apr 21, 2022
Priority date	Jun 29, 2018
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first transistor device region including a first source or drain contact structure on a semiconductor-containing source or drain region, the first source or drain contact structure including a metal body and a layer, the layer between the metal body and the semiconductor-containing source or drain region, the layer being compositionally different from the metal body and the semiconductor-containing source or drain region, and the layer including first and second portions, the first and second portions being collinear with each other and compositionally different from one another, wherein the first portion of the layer comprises a semiconductor and a metal, and the second portion comprises the semiconductor; and
a second transistor device region including a contact surface, the contact surface being part of a gate structure, or part of a second source or drain contact structure;
wherein the first and second transistor device regions are arranged in a vertically stacked configuration, and a conductive interconnect extends downward from the first source or drain contact structure to contact the contact surface.

2. The integrated circuit of claim 1 , wherein the first source or drain contact structure is part of a non-planar transistor that includes a body of semiconductor material.

3. The integrated circuit of claim 2 , wherein the body is a fin.

4. The integrated circuit of claim 2 , wherein the body is a nanowire or a nanoribbon.

5. The integrated circuit of claim 1 , wherein the first source or drain contact structure is part of a planar transistor that includes a body of semiconductor material.

6. The integrated circuit of claim 1 , further comprising insulator material under the semiconductor-containing source or drain region, the insulator material having as sidewall that is collinear with the first and second portions of the layer.

7. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first transistor device region including a first source or drain contact structure on a semiconductor-containing source or drain region, the first source or drain contact structure including a metal body and a layer, the layer between the metal body and the semiconductor-containing source or drain region, the layer being compositionally different from the metal body and the semiconductor-containing source or drain region, and the layer including first and second portions, the first and second portions being collinear with each other and compositionally different from one another, wherein the first portion of the layer comprises a semiconductor and a metal, and the second portion comprises the semiconductor; and
a second transistor device region including a contact surface, the contact surface being part of a gate structure, or part of a second source or drain contact structure;
wherein the first and second transistor device regions are arranged in a vertically stacked configuration, and a conductive interconnect extends downward from the first source or drain contact structure to contact the contact surface.

8. The computing device of claim 7 , further comprising:
a memory coupled to the board.

9. The computing device of claim 7 , further comprising:
a communication chip coupled to the board.

10. The computing device of claim 7 , further comprising:
a battery coupled to the board.

11. The computing device of claim 10 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

12. The computing device of claim 7 , wherein the component is a packaged integrated circuit die.

13. A method of fabricating an integrated circuit, the method comprising:
forming a first transistor device region including a first source or drain contact structure on a semiconductor-containing source or drain region, the first source or drain contact structure including a metal body and a layer, the layer between the metal body and the semiconductor-containing source or drain region, the layer being compositionally different from the metal body and the semiconductor-containing source or drain region, and the layer including first and second portions, the first and second portions being collinear with each other and compositionally different from one another, wherein the first portion of the layer comprises a semiconductor and a metal, and the second portion comprises the semiconductor; and
forming a second transistor device region including a contact surface, the contact surface being part of a gate structure, or part of a second source or drain contact structure;
wherein the first and second transistor device regions are arranged in a vertically stacked configuration, and a conductive interconnect extends downward from the first source or drain contact structure to contact the contact surface.

14. The method of claim 13 , wherein the first source or drain contact structure is part of a non-planar transistor that includes a body of semiconductor material.

15. The method of claim 14 , wherein the body is a fin.

16. The method of claim 14 , wherein the body is a nanowire or a nanoribbon.

17. The method of claim 13 , wherein the first source or drain contact structure is part of a planar transistor that includes a body of semiconductor material.

18. The method of claim 13 , further comprising insulator material under the semiconductor-containing source or drain region, the insulator material having as sidewall that is collinear with the first and second portions of the layer.

Assignees

• Intel Corp

Inventors

• Lilak Aaron D
• Phan Anh
• Mannebach Ehren
• Huang Cheng-Ying
• Bojarski Stephanie A
• Dewey Gilbert
• Acton Orb
• Rachmady Willy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title