Stacked trigate transistors with dielectric isolation and process for forming such

Patent metadata

Field	Value
Publication number	US-11894372-B2
Application number	US-202318095973-A
Country	US
Kind code	B2
Filing date	Jan 11, 2023
Priority date	Jun 27, 2019
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

First claim

What is claimed is:

1. A method, comprising:
forming a semiconductor substrate;
forming a first semiconductor layer above the semiconductor substrate;
forming a second semiconductor layer above the first semiconductor layer;
patterning a first fin from portions of the semiconductor substrate, the first semiconductor layer and the second semiconductor layer;
forming a dummy gate material around the fin;
performing a selective etch that removes remaining portions of the first semiconductor layer to form an upper fin and a lower fin from the first fin;
forming a conformal dielectric layer on the upper and lower fin, between the upper and lower fin, and on the dummy gate material;
removing portions of the upper fin and the lower fin that are located on a first and a second side of the dummy gate that extend beyond the dummy gate; and
forming a dielectric isolation structure and gate spacers by removing portions of the conformal dielectric layer.

2. The method of claim 1 , wherein the dielectric isolation structure includes the same material that is included in the gate spacers.

3. The method of claim 1 , wherein forming the dielectric isolation structure includes forming material on opposing surfaces of the upper fin and the lower fin.

4. The method of claim 3 , wherein the material formed on opposing surfaces of the upper fin and the lower fin meet to fill the space between the upper fin and the lower fin.

5. The method of claim 4 , wherein the material formed on opposing surfaces of the upper fin and the lower fin meet to form an internal physical interface.

6. The method of claim 1 , wherein forming the dummy gate includes forming polysilicon around the fin.

7. The method of claim 1 , wherein the conformal dielectric layer includes SiN, SiON, SiCN, or SiOCN.

8. A method of fabricating a device, the method comprising:
forming a first semiconductor fin;
forming a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin;
forming a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin;
forming a first gate conductor above the first semiconductor fin;
forming a gate spacer covering the sides of the gate conductor;
forming a second semiconductor fin below the first semiconductor fin;
forming a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin;
forming a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin;
forming a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin; and
forming a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin and separating the first semiconductor fin and the second semiconductor fin.

9. The method of claim 8 , further comprising:
forming a first source-drain isolation structure between the first source-drain epitaxial region and the third source-drain epitaxial region and a second source-drain isolation structure between the second source-drain epitaxial region and the fourth source-drain epitaxial region.

10. The method of claim 8 , wherein the dielectric isolation structure includes the same material that is included in the gate spacer.

11. The method of claim 8 , wherein the dielectric isolation structure includes an internal physical interface.

12. The method of claim 8 , wherein the first source-drain epitaxial region and the second source-drain epitaxial region are isolated from the second fin.

13. The method of claim 8 , wherein the third source-drain epitaxial region and the fourth source-drain epitaxial region are isolated from the first fin.

14. The method of claim 8 , wherein the dielectric isolation structure includes a low-k material.

15. The method of claim 8 , wherein the thickness of the dielectric isolation structure is 10-50 nm.

16. The method of claim 8 , wherein the thickness of the first source-drain isolation structure and the second source-drain isolation structure is 5-50 nm.

17. A method of fabricating a system, the method comprising:
providing one or more processing components; and
coupling one or more data storage components to the one or more processing components, one or more of the processing components or the data storage components including at least one device, the at least one device fabricated according to a method including:
forming a first semiconductor fin;
forming a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin;
forming a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin;
forming a first gate conductor above the first semiconductor fin;
forming a gate spacer covering the sides of the gate conductor;
forming a second semiconductor fin below the first semiconductor fin;
forming a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin;
forming a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin;
forming a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin; and
forming a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin and separating the first semiconductor fin and the second semiconductor fin.

18. The method of claim 17 , wherein the dielectric isolation structure includes the same material that is included in the gate spacer.

19. The method of claim 17 , wherein the dielectric isolation structure includes an internal physical interface.

20. The method of claim 17 , wherein the first source-drain epitaxial region and the second source-drain epitaxial region are isolated from the second fin.

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Huang Cheng-Ying
• Dewey Gilbert
• Lilak Aaron
• Morrow Patrick
• Phan Anh
• Mannebach Ehren
• Kavalieros Jack T

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D86/215

  comprising FinFETs · CPC title