Metallization structures for stacked device connectivity and their methods of fabrication

Patent metadata

Field	Value
Publication number	US-11869894-B2
Application number	US-202217864264-A
Country	US
Kind code	B2
Filing date	Jul 13, 2022
Priority date	Mar 5, 2018
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a first device structure comprising:
a first body of semiconductor material comprising at least one of silicon or germanium; and
a plurality of terminals coupled with the first body; and

an insulator layer between the first device structure and an underlying second device structure, wherein the insulator layer comprises silicon and oxygen, and wherein the second device structure comprises:
a second body of semiconductor material comprising at least one of silicon or germanium;
a gate electrode coupled to the second body;
a spacer adjacent to a sidewall of the gate electrode;
a source or drain material coupled with the second body and between at least a portion of the spacer and the insulator layer, wherein the source or drain material comprises at least one of silicon or germanium and one or more donor or acceptor impurities, and;

a metallization structure in contact with the source or drain material, wherein the metallization structure extends through a thickness of the insulator layer and is coupled with one of the terminals of the first device structure.

2. The IC of claim 1 , wherein the metallization structure is in contact with a source or drain terminal of the first device structure.

3. The IC of claim 1 , wherein the insulator layer comprises silicon, oxygen, nitrogen, or carbon.

4. The IC of claim 1 , wherein at least a region of the insulator layer between the first device structure and the second device structure is substantially planar.

5. The IC of claim 4 , wherein a portion of the source and drain material is between the gate electrode and the insulator layer.

6. The IC of claim 1 , wherein the second body of semiconductor material is over the first body of semiconductor material and the terminals of the first device structure comprise a first gate electrode that is under the gate electrode of the second device structure.

7. The IC of claim 1 , wherein a portion of the source or drain material is laterally adjacent to a first portion of a sidewall of the insulator layer.

8. The IC of claim 7 , wherein the metallization structure is in contact with a second portion of the sidewall of the insulator layer, below the first portion of the sidewall.

9. The IC of claim 1 , wherein the metallization structure comprises an adhesion layer in contact with the source or drain material, and a fill layer adjacent to the adhesion layer.

10. The IC of claim 1 , wherein the metallization structure comprises at least one of titanium, tungsten, cobalt, ruthenium, titanium or a group III material.

11. The IC of claim 1 , further comprising a memory device coupled with the metallization structure, the memory device comprising a resistive memory device or a magnetic tunnel junction (MTJ) memory device.

12. A stacked transistor structure, comprising:
a first transistor under a second transistor with an intervening insulator layer therebetween, wherein the second transistor comprises:
a gate electrode over a channel material comprising at least one of silicon or germanium; and
a source or drain material coupled to the channel material and below a spacer that is adjacent to a sidewall of the gate electrode; and

a metallization structure in contact with the source or drain material, wherein the metallization structure extends through a thickness of the insulator layer and is coupled with a terminal of the first transistor.

13. The stacked transistor structure of claim 12 , wherein the source or drain material comprises two group IV elements.

14. The stacked transistor structure of claim 12 , wherein the metallization structure is in contact with a sidewall of the insulator layer.

15. A method of forming a stacked transistor structure, the method comprising:
receiving a workpiece comprising a semiconductor material separated from a lower transistor structure by an intervening insulator layer;
forming a semiconductor body comprising the semiconductor material;
forming a gate coupled to the semiconductor body;
forming a spacer adjacent to the gate;
forming an opening through the insulator layer and removing a portion of the semiconductor body adjacent to the spacer, the opening further exposing a terminal of the lower transistor structure;
laterally recessing a sidewall of the semiconductor body;
forming a source or drain material in contact with the sidewall of the semiconductor body; and
forming a metallization structure in the opening, the metallization structure in contact with the source or drain material, and in contact with the terminal of the lower transistor structure.

16. The method of claim 15 , wherein:
laterally recessing the sidewall of the semiconductor body undercuts a portion of the gate; and
forming the source or drain material at least partially fills in an undercut portion of the gate.

17. The method of claim 16 , wherein:
forming the metallization structure further comprises forming metallization in contact with a sidewall of the insulator layer; and
forming the source or drain material further comprises laterally extending the source or drain material beyond the sidewall of the insulator layer.

18. The method of claim 15 , wherein forming the opening through the insulator layer comprises exposing a contact metallization of the lower transistor structure.

19. The method of claim 15 , wherein the semiconductor material comprises silicon or germanium.

20. The method of claim 19 , wherein the source or drain material comprises two group IV elements.

Assignees

• Intel Corp

Inventors

• Lilak Aaron D
• Phan Anh
• Morrow Patrick
• Rachmady Willy
• Dewey Gilbert
• Torres Jessica M
• Jun Kimin
• Tronic Tristan A
• Jezewski Christopher J
• Yoo Hui Jae
• Chau Robert S
• Tsang Chi-Hwa

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title