Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Patent metadata

Field	Value
Publication number	US-12107085-B2
Application number	US-202318219374-A
Country	US
Kind code	B2
Filing date	Jul 7, 2023
Priority date	Jun 29, 2018
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first transistor device layer including a first gate structure, a first source or drain region adjacent the first gate structure and comprising a first semiconductor material, and a contact structure on the first source or drain region, the first source or drain region having a lateral width along a direction; and
a second transistor device layer including a second gate structure, and a second source or drain region adjacent the second gate structure and comprising a second semiconductor material, the second source or drain region having a lateral width along the direction greater than the lateral width of the first source or drain region along the direction;
wherein the first and second transistor device layers are arranged in a vertically stacked configuration, and the contact structure is vertically between the first source or drain region and the second semiconductor material of the second source or drain region.

2. The integrated circuit structure of claim 1 , further comprising an etch stop layer vertically between the contact structure and the second semiconductor material of the second source or drain region.

3. The integrated circuit structure of claim 1 , further comprising an isolation wall within the first transistor device layer, the contact structure on the first source or drain region being laterally adjacent to the isolation wall, and/or an isolation wall within the second transistor device layer, the second semiconductor material of the second source or drain region being laterally adjacent to the isolation wall.

4. The integrated circuit structure of claim 3 , wherein one or both of the isolation walls within the first and second transistor device layers comprises one or more first insulator materials that provide etch selectivity with respect to a second insulator material adjacent to the one or both of the isolation walls.

5. The integrated circuit structure of claim 1 , further comprising a bonding layer in the second transistor device layer, the second semiconductor material of the second source or drain region being laterally adjacent to the bonding layer.

6. The integrated circuit structure of claim 1 , wherein the contact structure on the first source or drain region is a first contact structure, the integrated circuit structure further comprising a second contact structure on an upper surface of the second source or drain region.

7. The integrated circuit structure of claim 1 , wherein the first and second transistor device layers include non-planar transistor architecture, including one or more of a semiconductor fin, nanowire, and/or nanoribbon.

8. The integrated circuit structure of claim 1 , wherein the first and second gate structures each include a gate electrode and a gate dielectric between the gate electrode and a corresponding gated region, and wherein the gate dielectrics comprise a high-k dielectric material.

9. The integrated circuit structure of claim 1 , wherein the first semiconductor material of the first source or drain region comprises a group III-V semiconductor material, and the second semiconductor material of the second source or drain region comprises a group IV semiconductor material.

10. The integrated circuit structure of claim 1 , wherein first source or drain region comprises an n-type dopant, and the second source or drain region comprises a p-type dopant.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first transistor device layer including a first gate structure, a first source or drain region adjacent the first gate structure and comprising a first semiconductor material, and a contact structure on the first source or drain region, the first source or drain region having a lateral width along a direction; and
a second transistor device layer including a second gate structure, and a second source or drain region adjacent the second gate structure and comprising a second semiconductor material, the second source or drain region having a lateral width along the direction greater than the lateral width of the first source or drain region along the direction;
wherein the first and second transistor device layers are arranged in a vertically stacked configuration, and the contact structure is vertically between the first source or drain region and the second semiconductor material of the second source or drain region.

12. The computing device of claim 11 , further comprising an etch stop layer vertically between the contact structure and the second semiconductor material of the second source or drain region.

13. The computing device of claim 11 , wherein the contact structure is in contact with the second semiconductor material of the second source or drain region.

14. The computing device of claim 11 , further comprising:
a memory coupled to the board.

15. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

16. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

17. The computing device of claim 11 , further comprising:
a battery coupled to the board.

18. The computing device of claim 11 , further comprising:
a display coupled to the board.

19. The computing device of claim 11 , further comprising:
a camera coupled to the board.

20. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Lilak Aaron D
• Dewey Gilbert
• Huang Cheng-Ying
• Jezewski Christopher
• Mannebach Ehren
• Mehandru Rishabh
• Morrow Patrick
• Murthy Anand S
• Phan Anh
• Rachmady Willy

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W72/353

  not comprising solid metals or solid metalloids, e.g. ceramics · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title