Sideways vias in isolation areas to contact interior layers in stacked devices

Patent metadata

Field	Value
Publication number	US-12255137-B2
Application number	US-202418419015-A
Country	US
Kind code	B2
Filing date	Jan 22, 2024
Priority date	Jun 28, 2019
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first stack, wherein the first stack comprises:
a plurality of first components; and
a first plurality of insulating layers, wherein the plurality of first components are electrically isolated from each other by the first plurality of insulating layers;

an isolation region adjacent to the first stack, wherein the isolation region comprises:
a first wall that contacts a sidewall of the first stack;
a second wall that is parallel to the first wall; and
a fill layer between the first wall and the second wall; and
a via, wherein the via comprises:
a first portion between the first wall and the second wall that extends in a vertical direction; and
a second portion that extends away from the first portion, wherein the second portion passes through the first wall and contacts one of the plurality of first components.

2. The semiconductor device of claim 1 , wherein the via further comprises:
a plurality of second portions that extend away from the first portion, wherein each second portion of the plurality of second portions contacts a different one of the plurality of first components.

3. The semiconductor device of claim 1 , wherein the via extends through an entire thickness of the fill layer.

4. The semiconductor device of claim 1 , wherein the plurality of first components comprises one or more of a capacitor, an inductor, a transistor, and a diode.

5. The semiconductor device of claim 1 , further comprising:
a second stack adjacent to the second wall of the isolation region, wherein the second stack comprises:
a plurality of second components; and
a second plurality of insulating layers, wherein the plurality of second components are electrically isolated from each other by the second plurality of insulating layers.

6. The semiconductor device of claim 5 , wherein the via further comprises:
a third portion that extends away from the first portion, wherein the third portion passes through the second wall and contacts one of the plurality of second components.

7. The semiconductor device of claim 6 , wherein the one of the plurality of second components is at a same Z-height as the one of the plurality of first components, or wherein the one of the plurality of second components is at a different Z-height as the one of the plurality of first components.

8. The semiconductor device of claim 6 , wherein the first stack of components is aligned along a first Y-Z plane and the second stack of component is aligned along a second Y-Z plane that is different than the first Y-Z plane.

9. An electronic system, comprising:
a board;
a package substrate electrically coupled to the board; and
a die electrically coupled to the package substrate, wherein the die comprises:
a first stack, wherein the first stack comprises:
a plurality of first components; and
a first plurality of insulating layers, wherein the plurality of first components are electrically isolated from each other by the first plurality of insulating layers;

an isolation region adjacent to the first stack, wherein the isolation region comprises:
a first wall that contacts a sidewall of the first stack;
a second wall that is parallel to the first wall; and
a fill layer between the first wall and the second wall; and

a via, wherein the via comprises:
a first portion between the first wall and the second wall that extends in a vertical direction; and
a second portion that extends away from the first portion, wherein the second portion passes through the first wall and contacts one of the plurality of first components.

10. The electronic system of claim 9 , further comprising:
a memory coupled to the board.

11. The electronic system of claim 9 , further comprising:
a communication chip coupled to the board.

12. The electronic system of claim 9 , further comprising:
a battery coupled to the board.

Assignees

• Intel Corp

Inventors

• Mannebach Ehren
• Lilak Aaron
• Yoo Hui Jae
• Morrow Patrick
• Phan Anh
• Rachmady Willy
• Huang Cheng-Ying
• Dewey Gilbert
• Mehandru Rishabh

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title