Stacked source-drain-gate connection and process for forming such

Patent metadata

Field	Value
Publication number	US-12148806-B2
Application number	US-202418408346-A
Country	US
Kind code	B2
Filing date	Jan 9, 2024
Priority date	Jun 27, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a semiconductor body having a channel region;
a gate structure over the channel region of the fin;
a first epitaxial source or drain structure at a side of the channel region of the semiconductor body;
a second epitaxial source or drain structure at the side of the channel region of the semiconductor body, the second epitaxial source or drain structure vertically over the first epitaxial source or drain structure;
a contact conductor on a top of the second epitaxial source or drain structure; and
a conductive via extending from a location beneath a bottom of the first epitaxial source or drain structure, through the first epitaxial source or drain structure, and to a bottom of the second epitaxial source or drain structure.

2. The integrated circuit structure of claim 1 , wherein the second epitaxial source or drain structure is vertically spaced apart from the first epitaxial source or drain structure.

3. The integrated circuit structure of claim 2 , wherein the second epitaxial source or drain structure is vertically separated from the first epitaxial source or drain structure by a dielectric structure.

4. The integrated circuit structure of claim 3 , and wherein the conductive via extends through the dielectric structure.

5. The integrated circuit structure of claim 1 , wherein the gate structure comprises a first gate electrode, and a second gate electrode vertically over the first gate electrode.

6. The integrated circuit structure of claim 5 , wherein the first gate electrode is in contact with the second gate electrode.

7. The integrated circuit structure of claim 1 , further comprising:
a dielectric spacer between the first epitaxial source or drain structure and the gate structure, and between the second epitaxial source or drain structure and the gate structure.

8. The integrated circuit structure of claim 1 , further comprising:
a spacer on the bottom of the first epitaxial source or drain structure, the spacer laterally adjacent to the conductive via.

9. The integrated circuit structure of claim 1 , wherein the semiconductor body comprises a fin.

10. The integrated circuit structure of claim 1 , wherein the semiconductor body comprises a nanowire.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor body having a channel region;
a gate structure over the channel region of the fin;
a first epitaxial source or drain structure at a side of the channel region of the semiconductor body;
a second epitaxial source or drain structure at the side of the channel region of the semiconductor body, the second epitaxial source or drain structure vertically over the first epitaxial source or drain structure;
a contact conductor on a top of the second epitaxial source or drain structure; and
a conductive via extending from a location beneath a bottom of the first epitaxial source or drain structure, through the first epitaxial source or drain structure, and to a bottom of the second epitaxial source or drain structure.

12. The computing device of claim 11 , wherein the semiconductor body comprises a fin.

13. The computing device of claim 11 , wherein the semiconductor body comprises a nanowire.

14. The computing device of claim 11 , further comprising:
a memory coupled to the board.

15. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

16. The computing device of claim 11 , further comprising:
a battery coupled to the board.

17. The computing device of claim 11 , further comprising:
a camera coupled to the board.

18. The computing device of claim 11 , further comprising:
a display coupled to the board.

19. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

20. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Mannebach Ehren
• Lilak Aaron
• Yoo Hui Jae
• Morrow Patrick
• Phan Anh
• Rachmady Willy
• Huang Cheng-Ying
• Dewey Gilbert

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10D64/258 Primary

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title