Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach

Patent metadata

Field	Value
Publication number	US-11830933-B2
Application number	US-201916240369-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Jan 4, 2019
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a substrate, the vertical arrangement of nanowires having one or more active nanowires above one or more oxidized nanowires, wherein the one or more oxidized nanowires are inactive nanowires;
a gate stack over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

2. The integrated circuit structure of claim 1 , wherein the one or more oxidized nanowires have an oxidation catalyst layer thereon.

3. The integrated circuit structure of claim 2 , wherein the oxidation catalyst layer comprises aluminum oxide.

4. The integrated circuit structure of claim 1 , further comprising:
epitaxial source or drain structures at ends of the vertical arrangement of nanowires.

5. The integrated circuit structure of claim 4 , wherein the epitaxial source or drain structures are discrete epitaxial source or drain structures.

6. The integrated circuit structure of claim 4 , wherein the epitaxial source or drain structures are non-discrete epitaxial source or drain structures.

7. The integrated circuit structure of claim 4 , wherein the gate stack has dielectric sidewall spacers, and the epitaxial source or drain structures are embedded epitaxial source or drain structures extending beneath the dielectric sidewall spacers of the gate stack.

8. The integrated circuit structure of claim 4 , further comprising:
a pair of conductive contact structures coupled to the epitaxial source or drain structures.

9. The integrated circuit structure of claim 8 , wherein the pair of conductive contact structures is an asymmetric pair of conductive contact structures.

10. The integrated circuit structure of claim 1 , wherein the vertical arrangement of nanowires is over a fin.

11. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Dewey Gilbert
• Kavalieros Jack T
• Lilak Aaron
• Morrow Patrick
• Phan Anh
• Huang Cheng-Ying
• Mannebach Ehren

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title