Epitaxial layer with substantially parallel sides

Patent metadata

Field	Value
Publication number	US-12020929-B2
Application number	US-201916454568-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Jun 27, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
an epitaxial layer with a first side and a second side opposite the first side;
wherein the first side and the second side of the epitaxial layer are substantially planar;
wherein the second side of the epitaxial layer is substantially parallel to the first side;
wherein the first side of the epitaxial layer is directly coupled with a side of the substrate;
a first oxide layer having a first side and a second side opposite the first side, wherein the first side of the first oxide layer is on the second side of the epitaxial layer, wherein a first width of the epitaxial layer at an uppermost side of the epitaxial layer adjacent to the first side of the first oxide layer is less than a second width of the epitaxial layer located between the first side and the second side of the epitaxial layer;
a silicon layer on the second side of the first oxide layer; and
a second oxide layer on an edge of the epitaxial layer, wherein the second oxide layer extends from the first side of the epitaxial layer to the second side of the epitaxial layer, and wherein the second oxide layer is non-planar.

2. The apparatus of claim 1 , wherein the epitaxial layer is a grown silicon germanium (SiGe) layer or a grown silicon (Si) layer.

3. The apparatus of claim 1 , wherein the epitaxial layer is a grown layer between the side of the substrate and the first side of the first oxide layer.

4. The apparatus of claim 1 , wherein the second side of the first oxide layer is directly coupled with the silicon layer.

5. The apparatus of claim 4 , wherein the apparatus is a portion of a transistor, wherein the epitaxial layer is either an N-type or a P-type, wherein the silicon layer is either an N-type or a P-type, and wherein the first oxide layer is an electrical separation layer.

6. A system comprising:
an interconnect layer;
a transistor coupled with the interconnect layer, the transistor including:
a substrate;
an epitaxial layer with a first side and a second side opposite the first side;
wherein the first side and the second side of the epitaxial layer are substantially planar;
wherein the second side of the epitaxial layer is substantially parallel to the first side;
wherein the first side of the epitaxial layer is directly coupled with a side of the substrate;
a first oxide layer with a first side and a second side opposite the first side, wherein the first side of the first oxide layer is on the second side of the epitaxial layer, wherein a first width of the epitaxial layer at an uppermost side of the epitaxial layer adjacent to the first side of the first oxide layer is less than a second width of the epitaxial layer located between the first side and the second side of the epitaxial layer;

a silicon layer on the second side of the first oxide layer; and
a second oxide layer on an edge of the epitaxial layer, wherein the second oxide layer extends from the first side of the epitaxial layer to the second side of the epitaxial layer, and wherein the second oxide layer is non-planar.

7. The system of claim 6 , wherein the epitaxial layer is a grown silicon germanium (SiGe) layer or a grown silicon (Si) layer.

8. The system of claim 6 , wherein two or more sides of the epitaxial layer are at least partially coated in an isolation oxide.

9. The system of claim 6 ,
wherein the second side of the epitaxial layer is directly coupled with the first side of the first oxide layer.

10. The system of claim 6 , wherein the epitaxial layer is grown between the side of the substrate and the first side of the first oxide layer.

11. The system of claim 6 , wherein the second side of the first oxide layer is directly coupled with the silicon layer, and wherein the epitaxial layer is either an N-type or a P-type, the silicon layer is either an N-type or a P-type, and the first oxide layer is an electrical separation layer.

Assignees

• Intel Corp

Inventors

• Huang Cheng-Ying
• Dewey Gilbert
• Kavalieros Jack T
• Lilak Aaron
• Mannebach Ehren
• Morrow Patrick
• Phan Anh
• Rachmady Willy
• Yoo Hui Jae

Classifications

• H10P14/3226

  Oxides · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title