Semiconductor device with reduced via resistance
US-11222815-B2 · Jan 11, 2022 · US
This page is not indexed by search engines while we improve data quality.
Murray Conal E patents
Murray Conal E is listed as an inventor on 57 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Murray Conal E |
| Total patents | 57 |
| First publication | Jun 16, 2015 |
| Latest publication | Jan 11, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Semiconductor device with reduced via resistance
US-2021183699-A1 · Jun 17, 2021 · US
Semiconductor device with reduced via resistance
US-10804147-B2 · Oct 13, 2020 · US
Reducing contact resistance in vias for copper interconnects
US-10714379-B2 · Jul 14, 2020 · US
Semiconductor device with reduced via resistance
US-2020090993-A1 · Mar 19, 2020 · US
Semiconductor device with reduced via resistance
US-2020090994-A1 · Mar 19, 2020 · US
Reducing contact resistance in vias for copper interconnects
US-2020066576-A1 · Feb 27, 2020 · US
Semiconductor device with reduced via resistance
US-10553483-B2 · Feb 4, 2020 · US
Reducing contact resistance in vias for copper interconnects
US-10468296-B2 · Nov 5, 2019 · US
Hybrid interconnects and method of forming the same
US-10446491-B2 · Oct 15, 2019 · US
Recent patents
Latest publications not already listed above.
Method for forming improved liner layer and semiconductor device including the same
US-10424504-B2 · Sep 24, 2019 · US
Activating reactions in integrated circuits through electrical discharge
US-10388615-B2 · Aug 20, 2019 · US
Reducing contact resistance in vias for copper interconnects
US-10361115-B2 · Jul 23, 2019 · US
Activating reactions in integrated circuits through electrical discharge
US-10262955-B2 · Apr 16, 2019 · US
Forming a stacked capacitor
US-10242943-B2 · Mar 26, 2019 · US
Reducing contact resistance in vias for copper interconnects
US-10170358-B2 · Jan 1, 2019 · US
Semiconductor device interconnect structures formed by metal reflow process
US-10109586-B2 · Oct 23, 2018 · US
Capacitance monitoring using x-ray diffraction
US-10008421-B2 · Jun 26, 2018 · US
Semiconductor device with reduced via resistance
US-2018174903-A1 · Jun 21, 2018 · US
Columnar interconnects and method of making them
US-9997406-B2 · Jun 12, 2018 · US
Activating reactions in integrated circuits through electrical discharge
US-9991214-B2 · Jun 5, 2018 · US
Forming a Stacked Capacitor
US-2018122740-A1 · May 3, 2018 · US
Semiconductor device with reduced via resistance
US-9953869-B2 · Apr 24, 2018 · US
Capacitance monitoring using x-ray diffraction
US-2018096904-A1 · Apr 5, 2018 · US
Treating copper interconnects
US-9929092-B2 · Mar 27, 2018 · US
Activating reactions in integrated circuits through electrical discharge
US-2018061782-A1 · Mar 1, 2018 · US
Forming a stacked capacitor
US-9875959-B2 · Jan 23, 2018 · US
Method for forming improved liner layer and semiconductor device including the same
US-2018019164-A1 · Jan 18, 2018 · US
Method for forming improved liner layer and semiconductor device including the same
US-2018019163-A1 · Jan 18, 2018 · US
Capacitance monitoring using X-ray diffraction
US-9870960-B2 · Jan 16, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 52 |
| Globalfoundries Inc | 4 |
| Tessera Inc | 3 |
| Hsu Louis C | 1 |
| Murray Conal E | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/42 | 32 |
| H10W20/425 | 30 |
| H01L23/5226 | 30 |
| H10W20/43 | 27 |
| H10W20/089 | 25 |