Method for forming improved liner layer and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10424504-B2
Application number	US-201715705426-A
Country	US
Kind code	B2
Filing date	Sep 15, 2017
Priority date	Jul 14, 2016
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N2) and ammonia (NH3) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200. Watts to about 4500. Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening.

First claim

We claim:

1. A semiconductor device, comprising:
a dielectric layer;
an opening formed in the dielectric layer;
a liner layer on sidewall and bottom surfaces of the opening; and
a conductive layer on the liner layer in the opening;
wherein the liner layer comprises titanium nitride;
wherein a bottom portion of the liner layer on the bottom surface of the opening directly contacts a first dielectric material and side portions of the liner layer on the sidewall surfaces of the opening directly contact a second dielectric material different from the first dielectric material; and wherein the liner layer is a halogen diffusion barrier.

2. The semiconductor device according to claim 1 , wherein the liner layer and the conductive layer form at least part of an interconnect.

3. The semiconductor device according to claim 1 , wherein the liner layer and the conductive layer form at least part of a gate structure.

4. The semiconductor device according to claim 3 , wherein the liner layer is formed on a gate dielectric.

5. The semiconductor device according to claim 3 , wherein the liner layer is formed on a gate spacer.

6. The semiconductor device according to claim 1 , wherein a thickness of the liner layer is in a range of about 5 angstroms to about 20 nm.

7. The semiconductor device according to claim 6 , wherein a thickness of the liner layer is in a range of about 5 nm to about 10 nm.

8. The semiconductor device according to claim 1 , wherein the liner layer further is an oxygen diffusion barrier.

9. The semiconductor device according to claim 1 , wherein the liner layer further is a copper diffusion barrier.

10. The semiconductor device according to claim 1 , wherein the liner layer further is an oxygen, halogen and copper diffusion barrier.

11. A semiconductor device, comprising:
a dielectric layer;
an opening formed in the dielectric layer;
a liner layer conformally formed on a plurality of surfaces of the opening; and
a conductive layer on the liner layer in the opening;
wherein the liner layer comprises titanium nitride;
wherein a bottom portion of the liner layer on a bottom surface of the opening directly contacts a first dielectric material and side portions of the liner layer on sidewall surfaces of the opening directly contact a second dielectric material different from the first dielectric material; and wherein the liner layer is a halogen diffusion barrier.

12. The semiconductor device according to claim 11 , wherein the liner layer and the conductive layer form at least part of an interconnect.

13. The semiconductor device according to claim 11 , wherein the liner layer and the conductive layer form at least part of a gate structure.

14. The semiconductor device according to claim 11 , wherein a thickness of the liner layer is in a range of about 5 angstroms to about 20 nm.

15. The semiconductor device according to claim 14 , wherein a thickness of the liner layer is in a range of about 5 nm to about 10 nm.

16. The semiconductor device according to claim 11 , wherein the liner layer further is an oxygen diffusion barrier.

17. The semiconductor device according to claim 11 , wherein the liner layer further is a copper diffusion barrier.

18. The semiconductor device according to claim 11 , wherein the liner layer further is an oxygen and copper diffusion barrier.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/0526 Primary

  by thermal treatment thereof · CPC title

• H01L21/76864 Primary

  Electricity · mapped topic