Semiconductor device with reduced via resistance

Patent metadata

Field	Value
Publication number	US-9953869-B2
Application number	US-201615078066-A
Country	US
Kind code	B2
Filing date	Mar 23, 2016
Priority date	Jul 24, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

First claim

What is claimed:

1. A semiconductor interconnect structure comprising:
an electrically conductive structure that extends from a first interconnect level into a second interconnect level that is below the first interconnect level, the electrically conductive structure having a first portion in the first interconnect level;
a dielectric capping layer, wherein at least a portion of the dielectric capping layer is horizontally planar with and abuts a horizontal surface of the first portion of the electrically conductive structure, the portion of the dielectric capping layer being between the first interconnect level and the second interconnect level; and
a second portion of the electrically conductive structure in the second interconnect level, the second portion being vertically offset with the first portion such that a top surface of the second portion is below the first portion and a bottom surface of the dielectric capping layer.

2. The semiconductor interconnect structure of claim 1 , the structure further comprising:
a first dielectric layer located over the capping layer, the first dielectric layer having the first portion of the electrically conductive structure embedded therein, wherein the first portion of the electrically conductive structure includes a first liner material on one or more sidewalls of the first portion of the electrically conductive structure, and wherein the first portion of the electrically conductive structure is in electrical contact with at least one portion of a top surface of the second portion of the electrically conductive structure;
a second dielectric layer having the second portion of the electrically conductive structure embedded therein; and
a capping layer located over a portion of the second dielectric layer, the capping layer comprising at least one portion of a metal capping layer and the at least one portion of the dielectric capping layer, wherein the metal capping layer is located over at least a portion of the second portion of the electrically conductive structure, and wherein the dielectric capping layer is located over at least a portion of the second dielectric layer.

3. The semiconductor interconnect structure of claim 2 , wherein the metal capping layer comprises at least one layer comprising one or more of: Co, Ru, W, Ta, Ti, P, and Rh.

4. The semiconductor interconnect structure of claim 2 , wherein the dielectric capping layer comprises a dielectric material that inhibits metal diffusion between the first portion of the electrically conductive structure and the first dielectric layer.

5. The semiconductor interconnect structure of claim 2 ,
wherein the first portion of the electrically conductive structure has (I) a first bottom portion with the horizontal surface that abuts the dielectric capping layer and (II) a second bottom portion that is (i) within an opening through the metal capping layer and the first liner material and (ii) connects the first portion of the electrically conductive structure to the second portion of the electrically conductive structure.

6. The semiconductor interconnect structure of claim 2 , wherein the first portion of the electrically conductive structure further comprises a second liner material located over at least a portion of one or both of the first liner material and the dielectric capping layer, and is in contact with the top surface of the second portion of the electrically conductive structure.

7. The semiconductor interconnect structure of claim 6 , wherein the second liner material comprises at least one layer comprising a conductive material with low resistivity including one or more of: Cu, Co, and Ru.

8. The semiconductor interconnect structure of claim 7 , wherein low resistivity is defined as resistivity less than 100 micro-ohm centimeters.

9. The semiconductor interconnect structure of claim 1 , wherein the dielectric capping layer comprises at least one layer including one or more of: SiC, Si 4 NH 3 , and SiO 2 .

10. The semiconductor interconnect structure of claim 1 , wherein one or both of the first portion of the electrically conductive structure and the second portion of the electrically conductive structure comprise Cu.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title