Forming a stacked capacitor

Patent metadata

Field	Value
Publication number	US-9875959-B2
Application number	US-201615178245-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Jun 9, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Stacked capacitor structures using TSVs are provided. In one aspect, a stacked capacitor structure includes: a first substrate having at least one first capacitor formed in a TSV in the first substrate; and a second substrate, bonded to the first substrate, having at least one second capacitor formed in a TSV in the second substrate, wherein the first capacitor and the second capacitor each comprises a first electrode and a dielectric that both surround a second electrode that is at a core of the TSV, wherein the dielectric separates the first electrode from the second electrode, and wherein the second substrate is bonded to the first substrate such that the first capacitor is stacked on the second capacitor. A method of forming a stacked capacitor structure is also provided.

First claim

What is claimed is:

1. A method of forming a stacked capacitor structure, comprising:
forming at least one first capacitor in a TSV in a first substrate;
forming at least one second capacitor in a TSV in a second substrate, wherein the first capacitor and the second capacitor each comprises a first electrode and a dielectric that both surround a second electrode that is at a core of the TSV, and wherein the dielectric separates the first electrode from the second electrode, the method further comprising: selectively masking the second electrode in the second capacitor and recessing the first electrode of the second capacitor below a top surface of the second electrode of the second capacitor; and
bonding the second substrate to the first substrate such that the first capacitor is stacked on the second capacitor with continuity between the second electrode of the first capacitor and the second electrode of the second capacitor but, by way of the recessing, with the second electrode of the first capacitor being in a non-contact position with the first electrode of the second capacitor when the first capacitor is stacked on the second capacitor.

2. The method of claim 1 , further comprising:
bonding the second substrate to the first substrate in a front-to-back manner.

3. The method of claim 1 , further comprising:
bonding the second substrate to the first substrate in a back-to-back manner.

4. The method of claim 1 , further comprising:
forming at least one first landing pad on a backside of the first substrate and at least one second landing pad on a backside of the second substrate.

5. The method of claim 4 , further comprising:
patterning at least one first via in the first substrate over the first landing pad;
patterning at least one second via in the second substrate over the second landing pad;
forming the first capacitor in the first via; and
forming the second capacitor in the second via.

6. The method of claim 5 , further comprising:
conformally depositing a first metal into the first via and the second via;
depositing the dielectric onto the first metal; and
filling the first via and the second via with a second metal, wherein the first metal forms the first electrode and the second metal forms the second electrode.

7. The method of claim 6 , further comprising:
exposing the first landing pad at a bottom of the first via; and
exposing the second landing pad at the bottom of the second via.

8. The method of claim 6 , wherein the recessing comprises:
recessing the second metal in the first via and the second via.

9. The method of claim 8 , further comprising:
filling recesses left by the recessing with a dielectric.

10. The method of claim 6 , further comprising:
electroplating the second metal into the first via and the second via.

11. The method of claim 6 , wherein the first metal is selected from the group consisting of: ruthenium, cobalt, iridium, gold, titanium, tantalum, and combinations thereof, and wherein the second metal comprises copper.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title