Forming a stacked capacitor

Patent metadata

Field	Value
Publication number	US-10242943-B2
Application number	US-201715847634-A
Country	US
Kind code	B2
Filing date	Dec 19, 2017
Priority date	Jun 9, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Stacked capacitor structures using TSVs are provided. In one aspect, a stacked capacitor structure includes: a first substrate having at least one first capacitor formed in a TSV in the first substrate; and a second substrate, bonded to the first substrate, having at least one second capacitor formed in a TSV in the second substrate, wherein the first capacitor and the second capacitor each comprises a first electrode and a dielectric that both surround a second electrode that is at a core of the TSV, wherein the dielectric separates the first electrode from the second electrode, and wherein the second substrate is bonded to the first substrate such that the first capacitor is stacked on the second capacitor. A method of forming a stacked capacitor structure is also provided.

First claim

What is claimed is:

1. A stacked capacitor structure, comprising:
a first substrate having at least one first capacitor formed in a through-substrate via (TSV) in the first substrate; and
a second substrate, bonded to the first substrate, having at least one second capacitor formed in a TSV in the second substrate,
wherein the first capacitor and the second capacitor each comprises a first electrode and a dielectric that both surround a second electrode that is at a core of the TSV, wherein the dielectric separates the first electrode from the second electrode, and wherein the second substrate is bonded to the first substrate such that the first capacitor is stacked on the second capacitor.

2. The stacked capacitor structure of claim 1 , wherein the second substrate is bonded to the first substrate in a front-to-back manner.

3. The stacked capacitor structure of claim 1 , wherein the second substrate is bonded to the first substrate in a back-to-back manner.

4. The stacked capacitor structure of claim 1 , wherein the first capacitor and the second capacitor each further comprises a landing pad in contact with the second electrode.

5. The stacked capacitor structure of claim 1 , wherein the first electrode comprises a metal selected from the group consisting of: ruthenium, cobalt, iridium, gold, titanium, tantalum, and combinations thereof.

6. The stacked capacitor structure of claim 1 , wherein the dielectric comprises a material selected from the group consisting of: silicon oxide, tantalum oxide, silicon nitride, phosphorous-doped silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium dioxide, hafnium oxide, aluminum oxide, and combinations thereof.

7. The stacked capacitor structure of claim 1 , wherein the dielectric comprises a material selected from the group consisting of: silicon dioxide (SiO 2 ), tantalum oxide (Ta 2 O 5 ), silicon nitride (SiN), phosphorous-doped SiN (PSiN x ), silicon oxynitride (SiON), silicon carbide (SiC), tantalum oxide (TaO 2 ), zirconium dioxide (ZrO 2 ), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and combinations thereof.

8. The stacked capacitor structure of claim 1 , wherein the dielectric comprises a high-κ material.

9. The stacked capacitor of claim 8 , wherein the high-κ material is selected from the group consisting of: ZrO 2 , HfO 2 , Al 2 O 3 , and combinations thereof.

10. The stacked capacitor structure of claim 1 , wherein the second electrode comprises copper.

11. The stacked capacitor structure of claim 1 , wherein the first substrate has multiple first capacitors.

12. The stacked capacitor structure of claim 1 , wherein the second substrate has multiple second capacitors.

13. The stacked capacitor structure of claim 1 , further comprising:
a first dielectric passivation layer on the first substrate through which the TSV in the first substrate passes; and
a second dielectric passivation layer on the second substrate through which the TSV in the second substrate passes.

14. The stacked capacitor structure of claim 13 , wherein the first dielectric passivation layer and the second dielectric passivation layer each comprises a material selected from the group consisting of: silicon nitride (SiN), silicon carbide (SiC), SiO 2 , and combinations thereof.

15. The stacked capacitor structure of claim 1 , wherein the first substrate and the second substrate each have a thickness of from about 50 μm to about 200 μm, and ranges therebetween.

16. The stacked capacitor structure of claim 1 , further comprising:
at least one first landing pad on a backside of the first substrate; and
at least one second landing pad on a backside of the second substrate.

17. The stacked capacitor structure of claim 16 , wherein the at least one first landing pad and the at least one second landing pad are formed from copper.

18. The stacked capacitor structure of claim 1 , further comprising:
a conformal adhesion layer lining the TSV in the first substrate and the TSV in the second substrate;
a conformal metallic liner disposed on the conformal adhesion layer.

19. The stacked capacitor structure of claim 18 , wherein the conformal adhesion layer comprises a material selected from the group consisting of: tantalum nitride (TiN), titanium nitride (TiN), tungsten nitride (WN), SiO 2 , SiN, and combinations thereof.

20. The stacked capacitor structure of claim 18 , wherein the conformal metallic liner comprises a material selected from the group consisting of: ruthenium (Ru), cobalt (Co), iridium (Ir), gold (Au), titanium (Ti), tantalum (Ta), and combinations thereof.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title