Hybrid interconnects and method of forming the same

Patent metadata

Field	Value
Publication number	US-10446491-B2
Application number	US-201715609594-A
Country	US
Kind code	B2
Filing date	May 31, 2017
Priority date	Jul 6, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.

First claim

We claim:

1. A semiconductor device, comprising:
at least one dielectric layer;
a trench formed in the at least one dielectric layer;
an interconnect structure formed in the trench, wherein the interconnect structure comprises:
a first conductive layer comprising a bottom portion on a bottom surface of the trench and upper side portions on lateral sidewall surfaces of the trench, and partially filling the trench;
a second conductive layer on the first conductive layer, and filling part of a remaining portion of the trench; and
a liner layer between the first conductive layer and the second conductive layer;

wherein the liner layer comprises one or more of cobalt, ruthenium, tungsten and nitrides thereof;
wherein the second conductive layer comprises a different material from the first conductive layer;
wherein a thickness of the bottom portion of the first conductive layer is greater than a thickness of the upper side portions of the first conductive layer; and
wherein the second conductive layer comprises columnar grain boundaries; and
an oxide layer on the bottom surface and on the lateral sidewall surfaces of the trench, wherein the oxide layer is positioned between, and in contact with, the at least one dielectric layer and the bottom and the upper side portions of the first conductive layer;
wherein the oxide layer is distinct from the at least one dielectric layer;
wherein an aspect ratio of the second conductive layer has a value that is determined to result in the columnar grain boundaries in the second conductive layer;
wherein the aspect ratio is defined as a height of the second conductive layer divided by a width of the second conductive layer; and
wherein the aspect ratio is less than or equal to 1.

2. The semiconductor device according to claim 1 , wherein the second conductive layer comprises copper.

3. The semiconductor device according to claim 1 , wherein the second conductive layer is positioned between the upper side portions of the first conductive layer.

4. The semiconductor device according to claim 3 , wherein the liner layer is between the upper side portions of the first conductive layer and the second conductive layer.

5. The semiconductor device according to claim 1 , wherein the first conductive layer comprises silver.

6. The semiconductor device according to claim 1 , wherein the oxide layer comprises a different material from a material of the at least one dielectric layer.

7. The semiconductor device according to claim 1 , wherein the liner layer is a single layer.

8. A semiconductor device, comprising:
at least one dielectric layer;
a trench formed in the at least one dielectric layer; and
an interconnect structure formed in the trench, wherein the interconnect structure comprises:
a first conductive layer comprising a bottom portion on a bottom surface of the trench and upper side portions on lateral sidewall surfaces of the trench, and partially filling the trench;
a second conductive layer on the first conductive layer and partially filling the trench; and
a liner layer between the first conductive layer and the second conductive layer;

wherein the liner layer comprises one or more of cobalt, ruthenium, tungsten and nitrides thereof;
wherein the second conductive layer comprises a different material from the first conductive layer;
wherein a thickness of the bottom portion of the first conductive layer is greater than a thickness of the upper side portions of the first conductive layer; and
wherein the second conductive layer comprises columnar grain boundaries; and
an oxide layer on the bottom surface and on the lateral sidewall surfaces of the trench, wherein the oxide layer is positioned between and in contact with, the at least one dielectric layer and the bottom and the upper side portions of the first conductive layer;
wherein the oxide layer is distinct from the at least one dielectric layers;
wherein an aspect ratio of the second conductive layer has a value that is determined to result in the columnar grain boundaries in the second conductive layer;
wherein the aspect ratio is defined as a height of the second conductive layer divided by a width of the second conductive layer; and
wherein the aspect ratio is less than or equal to 1.

9. The semiconductor device according to claim 8 , wherein the second conductive layer comprises copper.

10. The semiconductor device according to claim 8 , wherein the second conductive layer is positioned between the upper side portions of the first conductive layer.

11. The semiconductor device according to claim 10 , wherein the liner layer is between the upper side portions of the first conductive layer and the second conductive layer.

12. The semiconductor device according to claim 8 , wherein the first conductive layer comprises silver.

13. The semiconductor device according to claim 8 , wherein the oxide layer comprises a different material from a material of the at least one dielectric layer.

14. The semiconductor device according to claim 8 , wherein the liner layer is a single layer.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title