Reducing contact resistance in vias for copper interconnects

US10170358B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10170358-B2
Application numberUS-201514730581-A
CountryUS
Kind codeB2
Filing dateJun 4, 2015
Priority dateJun 4, 2015
Publication dateJan 1, 2019
Grant dateJan 1, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

First claim

Opening claim text (preview).

What is claimed is: 1. An interconnect structure comprising: an interlevel dielectric layer on an electrically conductive feature; an opening in the interlevel dielectric layer, the opening including a first width at a first depth into the interlevel dielectric layer, and a second width at a second depth that is greater than the first depth, wherein the second width is less than the first width of the opening and includes a portion of the opening that extends through the entirety of the interlevel dielectric layer into contact with the electrically conductive feature; a conformal metal nitride layer present on vertical and horizontal surfaces of the opening, wherein the metal nitride layer is present directly on the interlevel dielectric layer; a shield liner present over vertical sidewalls of the opening directly on the conformal metal nitride layer, wherein the conformal metal nitride layer is present between the interlevel dielectric layer and the shield liner; and a contact extending through the opening into direct contact with the shield liner, the conformal metal nitride layer, and the electrically conductive feature, wherein a gouge is present at the interface of the contact and the electrically conductive feature. 2. The interconnect structure of claim 1 , wherein the electrically conductive feature is a metal line. 3. The interconnect structure of claim 1 , wherein the via opening has a substantially circular or multi-sided cross section. 4. The interconnect structure of claim 1 , wherein the gouge includes angled sidewalls extending to a substantially planar base, or the gouge includes angled sidewalls extending to an apex at a base of the gouge. 5. The interconnect structure of claim 1 , wherein the shield liner is comprised of a dielectric or electrically conductive material. 6. The interconnect structure of claim 1 , wherein the shield liner has a thickness ranging from 3 nm to 150 nm. 7. The interconnect structure of claim 1 further comprising a conformal metal nitride layer present on vertical and horizontal surfaces of the opening.

Assignees

Inventors

Classifications

  • Copper alloys · CPC title

  • Barrier, adhesion or liner layers · CPC title

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

  • in via holes or trenches · CPC title

  • by selectively depositing, e.g. by using selective CVD or plating · CPC title

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What does patent US10170358B2 cover?
A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric l…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W20/083. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).