Columnar interconnects and method of making them

Patent metadata

Field	Value
Publication number	US-9997406-B2
Application number	US-201615015389-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Feb 4, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Disclosed herein is an interconnect structure, including: a dielectric material layer having a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than or equal to about 2.5; a diffusion barrier liner layer disposed in the cavity on the dielectric material; an optional crystallization seed layer disposed on the diffusion barrier liner layer; and a conductive material disposed on the crystallization seed layer when present and filling the opening. When the crystallization seed layer is not present the conductive material is disposed on the diffusion barrier liner.

First claim

What is claimed is:

1. A method of making an interconnect structure, the method comprising:
forming a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than about 2.5;
disposing a diffusion barrier liner layer within the cavity;
disposing a conductive material on a surface of the diffusion barrier liner layer to completely fill the cavity and form a layer on the dielectric material, the conductive material comprising polysilicon, silicon germanium (SiGe), an alloy thereof, a metal silicide thereof, or a combination comprising at least one of the foregoing; and
recrystallizing the conductive material such that grain boundaries of the conductive material are arranged substantially orthogonal to a current flow along the length of the cavity, each grain boundary spanning the width and height of the cavity.

2. The method of claim 1 , wherein the height to width ratio is about 0.1 to about 0.5.

3. The method of claim 1 , wherein the conductive material comprises copper and is disposed by electroplating.

4. The method of claim 1 , wherein after annealing the conductive material has an average grain size greater than the width of the opening.

5. The method of claim 1 , wherein the conductive material has a bamboo microstructure.

6. A method of making an interconnect structure, the method comprising:
forming a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than about 2.5;
disposing a diffusion barrier liner layer within the cavity;
disposing a crystallization seed layer on the diffusion barrier liner layer, the crystallization seed layer comprising Ir, an Ir alloy, Ru, or a Ru alloy;
disposing a conductive material on the crystallization seed layer to completely fill the cavity and form a layer on the dielectric material, the conductive material comprising polysilicon, silicon germanium (SiGe), an alloy thereof, a metal silicide thereof, or a combination comprising at least one of the foregoing; and
recrystallizing the conductive material such that grain boundaries of the conductive material are arranged substantially orthogonal to a current flow along the length of the cavity, each grain boundary spanning the width and height of the cavity.

7. The method of claim 6 , wherein the height to width ratio is about 0.1 to about 0.5.

8. The method of claim 6 , wherein after annealing the conductive material has an average grain size greater than the width.

9. The method of claim 6 , wherein the conductive material has a bamboo microstructure.

10. The method of claim 6 , wherein the conductive material comprises copper and is disposed by electroplating.

11. An interconnect structure, comprising:
a dielectric material layer comprising a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than or equal to about 2.5;
a diffusion barrier liner layer disposed in the cavity on the dielectric material; and
a conductive material disposed on a surface of the diffusion barrier liner to completely fill the cavity, the conductive material having grain boundaries arranged substantially orthogonal to a current flow along the length of the cavity, each grain boundary spanning the width and height of the cavity, the conductive material comprising polysilicon, silicon germanium (SiGe), an alloy thereof, a metal silicide thereof, or a combination comprising at least one of the foregoing.

12. The interconnect structure of claim 11 , further comprising a crystallization seed layer disposed between the diffusion barrier liner layer and the conductive material.

13. The interconnect structure of claim 11 , wherein the conductive material has an average grain size greater than the width of the opening.

14. The interconnect structure of claim 11 , wherein the conductive material has a bamboo microstructure.

15. The interconnect structure of claim 11 , wherein the conductive material comprises copper.

16. The interconnect structure of claim 11 , wherein the diffusion barrier liner layer comprises tantalum (Ta), titanium (Ti), cobalt (Co), tungsten, ruthenium (Ru), ruthenium tantalum (RuTa), their nitrides, or any combination thereof.

17. The interconnect structure of claim 11 , wherein the height to width ratio is about 0.5 to about 2.5.

18. The interconnect structure of claim 11 , wherein the conductive material is a conductive metal.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4432

  the principal metal being a noble metal, e.g. gold · CPC title

• H10W20/4405

  the principal metal being aluminium · CPC title

• H10W20/4421

  the principal metal being copper · CPC title