Treating copper interconnects

Patent metadata

Field	Value
Publication number	US-9929092-B2
Application number	US-201615349168-A
Country	US
Kind code	B2
Filing date	Nov 11, 2016
Priority date	Apr 4, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Techniques relate to treating metallic interconnects of semiconductors. A metallic interconnect is formed in a layer. A metallic cap is disposed on top of the metallic interconnect. Any metallic residue, formed during the disposing of the metallic cap, is converted into insulating material.

First claim

What is claimed is:

1. A semiconductor device having metallic interconnects, the semiconductor device comprising:
a metallic interconnect formed in a layer;
a metallic cap disposed on top of the metallic interconnect; and
insulating material formed at one or more locations on the layer, wherein the insulating material includes metallic residue that has been treated;
wherein the insulating material is selected from a group consisting of a silicide that is not conductive and a silicate that is not conductive.

2. The semiconductor device of claim 1 , wherein the insulating material is formed of a surface of the metallic residue.

3. The semiconductor device of claim 1 , wherein the insulating material is formed of an entirety of the metallic residue.

4. The semiconductor device of claim 1 , wherein the insulating material is formed of a surface of first ones of the metallic residue.

5. The semiconductor device of claim 4 , wherein the insulating material is formed of an entirety of second ones of the metallic residue.

6. The semiconductor device of claim 1 , wherein an outer lining of the metallic cap includes the insulating material.

7. The semiconductor device of claim 6 , wherein a conductive via is formed through the outer lining of the metallic cap to reach conductive material of the metallic cap.

8. The semiconductor device of claim 1 , wherein the insulating material includes an oxide.

9. The semiconductor device of claim 1 , wherein the layer is a dielectric.

10. The semiconductor device of claim 9 , wherein the layer has a dielectric constant less than 2.5.

11. The semiconductor device of claim 9 , wherein the layer has a dielectric constant of about 1.

12. The semiconductor device of claim 1 , wherein a barrier layer separates the metallic interconnect from the layer.

13. The semiconductor device of claim 12 , wherein the barrier layer is selected from the group consisting of Ta, Ti, Co, W, Ru, and combinations thereof.

14. The semiconductor device of claim 1 , wherein the metallic interconnect is selected from the group consisting of Cu, W, Al, Co, Ru, and combinations thereof.

15. The semiconductor device of claim 1 , wherein the metallic cap is selected from the group consisting of Co, Ru, and Mn.

16. The semiconductor device of claim 1 , wherein the metallic cap includes a first material and a second material; and
wherein the first material is Co and the second material is selected from the group consisting of W, P, and B.

17. The semiconductor device of claim 1 , wherein the metallic cap has a thickness ranging from 5 to 10 nanometers.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10P70/273

  the processing being a delineation of conductive layers, e.g. by RIE · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title